XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 65

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC05JB3
REV 1
OCRH
RESET
R/W
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
A software example of this procedure is shown below.
OCRH
$0016
OCRL
$0017
U = UNAFFECTED BY RESET
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
5. Enable interrupts by clearing the I bit in the condition code register.
reset:
reset:
($FFFC)
clears the OCF flag bit in the TSR.
$0012
W
W
R
R
TIMER CONTROL REG.
Figure 9-10. Timer Output Compare Block Diagram
Figure 9-11. Output Compare Registers (OCRH, OCRL)
OCRH7
OCRL7
BIT 7
U
U
OCRH ($0016)
OCRH6
OCRL6
16-BIT COMPARATOR
BIT 6
16-BIT COUNTER
U
U
November 5, 1998
OCRH5
OCRL5
BIT 5
16-BIT TIMER
OUTPUT COMPARE
(OCF)
U
U
OCRL ($0017)
TIMER STATUS REG.
OCRH4
OCRL4
BIT 4
U
U
OCRH3
OCRL3
GENERAL RELEASE SPECIFICATION
BIT 3
$0013
U
U
PORT-C LOGIC
OCRH2
OCRL2
BIT 2
U
U
OCRL
4
R/W
OCRH1
OCRL1
OCMPO (bit7 at $06)
BIT 1
MUX
U
U
MOTOROLA
INTERRUPT
INTERNAL
REQUEST
INTERNAL
(f
CLOCK
TIMER
OSC
OCRH0
DATA
OCRL0
BUS
BIT 0
OCMP
PC0/
U
U
2)
9-9