ATTINY12 ATMEL Corporation, ATTINY12 Datasheet - Page 84
ATTINY12
Manufacturer Part Number
ATTINY12
Description
8-bit AVR Microcontroller with 1K Byte Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY12.pdf
(91 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY12-8PC
Manufacturer:
ATM
Quantity:
27 705
Company:
Part Number:
ATTINY12-8PC
Manufacturer:
AD
Quantity:
56
Part Number:
ATTINY12-8PC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY12-8SC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATTINY12-8SI
Manufacturer:
ATMEL
Quantity:
1 729
Company:
Part Number:
ATTINY12-8SU
Manufacturer:
ATMEL
Quantity:
5
Company:
Part Number:
ATTINY128SC
Manufacturer:
ATMEL
Quantity:
7 373
Part Number:
ATTINY12L-4SC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY12L-4SU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
ATTINY12V-1SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Instruction Set Summary (Continued)
84
Mnemonics
DATA TRANSFER INSTRUCTIONS
LD
ST
MOV
LDI
IN
OUT
LPM
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
ATtiny11/12
Operands
Rd,Z
Z,Rr
Rd, Rr
Rd, K
Rd, P
P, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Description
Load Register Indirect
Store Register Indirect
Move Between Registers
Load Immediate
In Port
Out Port
Load Program Memory
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watch Dog Reset
Operation
Rd
(Z)
Rd
Rd
Rd
P
R0
I/O(P,b)
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0)
Rd(7)
Rd(n)
Rd(3..0)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
1
0
1
Rr
Rr(b)
1
0
1
0
1
0
0
1
0
1
0
1
0
(Z)
(Z)
Rr
Rr
P
K
Rd(n+1), Rd(7)
C, Rd(n+1)
C, Rd(n)
Rd(n+1), n = 0..6
T
1
0
Rd(n), Rd(0)
Rd(7..4), Rd(7..4)
1
0
Rd(n+1), C
Rd(n), C
0
0
Rd(3..0)
Rd(7)
Rd(0)
Flags
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
1006D–AVR–07/03
#Clocks
2
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1