P89LV51RD2 Philips Semiconductors, P89LV51RD2 Datasheet - Page 32

• Manufacturer Part Number: P89LV51RD2
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 14101
Product data
7.4.1 Capture mode
Table 21:
Table 22:
Not bit addressable; Reset value: XX000000B
Table 23:
In the Capture Mode there are two options which are selected by bit EXEN2 in
T2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in
T2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit.
Bit
7
6
5
4
3
2
1
0
Bit
7 to 2
1
0
Bit
Symbol
T2CON - Timer/Counter 2 control register (address C8H) bit description
T2MOD - Timer 2 mode control register (address C9H) bit allocation
T2MOD - Timer 2 mode control register (address C9H) bit description
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
-
T2OE
DCEN
7
-
Rev. 03 — 11 October 2004
6
-
Description
Timer 2 overflow flag set by a Timer 2 overflow and must be
cleared by software. TF2 will not be set when either RCLK or
TCLK = 1 or when Timer 2 is in Clock-out Mode.
Timer 2 external flag is set when Timer 2 is in capture, reload or
baud-rate mode, EXEN2 = 1 and a negative transition on T2EX
occurs. If Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
Receive clock flag. When set, causes the UART to use Timer 2
overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the UART to use Timer 2
overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload
to occur as a result of a negative transition on T2EX if Timer 2 is
not being used to clock the serial port. EXEN2 = 0 causes Timer 2
to ignore events at T2EX.
Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.
Timer or counter select. (Timer 2)
Capture/Reload flag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overflows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overflow.
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Timer 2 Output Enable bit. Used in programmable clock-out mode
only.
Down Count Enable bit. When set, this allows Timer 2 to be
configured as an up/down counter.
0 = internal timer (f
1 = External event counter (falling edge triggered; external
clock’s maximum rate = f
5
-
4
-
osc
8-bit microcontrollers with 80C51 core
/6)
OSC
3
/12
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LV51RD2
2
-
T2OE
1
DCEN
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0