P89LV51RD2 Philips Semiconductors, P89LV51RD2 Datasheet - Page 60

• Manufacturer Part Number: P89LV51RD2
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 58:
9397 750 14101
Product data
Mode
Idle Mode
Power-down
Mode
Power-saving modes
Initiated by
Software
(Set IDL bit in PCON)
MOV PCON, #01H;
Software
(Set PD bit in PCON)
MOV PCON, #02H;
7.12.1 Clock Input Options and Recommended Capacitor Values for Oscillator
7.12 System clock and clock options
Shown in
XTAL2), which can be configured for use as an on-chip oscillator.
When driving the device from an external clock source, XTAL2 should be left
disconnected and XTAL1 should be driven.
At start-up, the external oscillator may encounter a higher capacitive load at XTAL1
due to interaction between the amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal meets the V
specifications.
Crystal manufacturer, supply voltage, and other factors may cause circuit
performance to differ from one application to another. C1 and C2 should be adjusted
appropriately for each design.
crystal type for various frequencies
Table 59:
More specific information about on-chip oscillator design can be found in the
FlashFlex51 Oscillator Circuit Design Considerations application note.
Crystal
Quartz
Ceramic
Figure 28
Recommended values for C1 and C2 by crystal type
State of MCU
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is stopped.
ALE and PSEN signals at a
HIGH level during Idle. All
registers remain unchanged.
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW level during power -down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Rev. 03 — 11 October 2004
are the input and output of an internal inverting amplifier (XTAL1,
Table 59
shows the typical values for C1 and C2 vs.
C1 = C2
20 pF to 30 pF
40 pF to 50 pF
8-bit microcontrollers with 80C51 core
Exited by
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits idle mode,
after the ISR RETI instruction, program
resumes execution beginning at the
instruction following the one that invoked
idle mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware reset
restarts the device similar to a power-on
reset.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
ISR RETI instruction program resumes
execution beginning at the instruction
following the one that invoked Power-down
mode. A user could consider placing two or
three NOP instructions after the instruction
that invokes Power-down mode to eliminate
any problems. A hardware reset restarts the
device similar to a power-on reset.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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