MC9S12A256 Motorola, MC9S12A256 Datasheet - Page 120

• Manufacturer Part Number: MC9S12A256
• Description: MC9S12DT256 Device User Guide V03.03
• Manufacturer: Motorola

MC9S12DT256 Device User Guide — V03.03
In Table A-19 the timing characteristics for master mode are listed.
118
Num
(CPOL 0)
(CPOL 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
10
11
12
13
1
1
2
3
4
5
6
9
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
MISO
MOSI
SCK
SCK
SS
SCK Frequency
SCK Period
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
1
PORT DATA
9
Characteristic
Table A-19 SPI Master Mode Timing Characteristics
2
MASTER MSB OUT
4
5
MSB IN
Figure A-6 SPI Master Timing (CPHA=1)
1
2
6
4
2
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
Symbol
t
t
t
f
t
wsck
t
t
vsck
lead
t
t
t
vss
t
sck
sck
lag
t
su
ho
rfo
hi
rfi
1/2048
Min
20
—
—
—
—
—
—
—
2
8
8
13
13
MASTER LSB OUT
LSB IN
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
3
2048
Max
1 2
30
15
—
—
—
—
—
—
8
8
PORT DATA
Unit
f
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
bus
bus
sck
sck
sck