ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 9
ispPAC-CLK55xx
Manufacturer Part Number
ispPAC-CLK55xx
Description
In-System Programmable Clock Generator with Universal Fan-Out Buffer
Manufacturer
Lattice Semiconductor
Datasheet
1.ISPPAC-CLK55XX.pdf
(43 pages)
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Lattice Semiconductor
Programmable Input and Output Termination Characteristics
R
C
R
OUT
IN
IN
Symbol
Input Resistance
Input Capacitance
Output Resistance
Parameter
Rin=40Ω setting
Rin=45Ω setting
Rin=50Ω setting
Rin=55Ω setting
Rin=60Ω setting
Rin=65Ω setting
Rin=70Ω setting
Rout≈20Ω setting, VCCO=1.5V
Rout≈20Ω setting, VCCO=1.8V
Rout≈20Ω setting, VCCO=2.5V
Rout≈20Ω setting, VCCO=3.3V
Rout=40Ω setting
Rout=45Ω setting
Rout=50Ω setting
Rout=55Ω setting
Rout=60Ω setting
Rout=65Ω setting
Rout=70Ω setting
Conditions
9
ispClock5500 Family Data Sheet
Min.
38
42
48
51
55
60
62
35
40
45
49
53
58
63
—
—
—
—
—
Typ.
27
22
20
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
Max.
42
46
53
57
62
68
73
47
55
61
67
72
78
83
—
—
—
—
—
Units
pF
Ω
Ω
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