ispPAC-POWR607-01SN32I Lattice, ispPAC-POWR607-01SN32I Datasheet
ispPAC-POWR607-01SN32I
Specifications of ispPAC-POWR607-01SN32I
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ispPAC-POWR607-01SN32I Summary of contents
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... Industrial temperature range: -40°C to +85°C • 32-pin QFNS (Quad Flat-pack, No lead, Saw- singulated) package, lead-free option Description Lattice’s Power Manager II ispPAC-POWR607 is a gen- eral-purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system program- mable logic and analog functions implemented in non- 2 ® ...
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... CPLD. Four independently programmable timers also interface with the CPLD and can create delays and time-outs ranging from 32µ seconds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer the analog input channel comparators or the digital inputs. Figure 4-1. ispPAC-POWR607 Block Diagram IN1_PWRDN Pin Descriptions Number ...
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... Not applicable Not applicable 4-3 ispPAC-POWR607 Data Sheet Description PLD Logic Input 2. When not used, this pin should be tied to GND. JTAG Test Clock Input JTAG Test Data In - Internal Pull-up JTAG Test Data Out JTAG Test Mode Select - Internal Pull-up ...
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... VCCJ, TDI, TDO, TMS and TCK = open. Parameter Parameter Conditions pins MON IN_OUT[3:7] pins HVOUT[1:2] pins in open- drain mode (Note 1) Power applied Conditions ICC + pin leakage currents 4-4 ispPAC-POWR607 Data Sheet Conditions Min. Max. -0.5 4.5 -0.5 -0.5 -0.5 HVOUT[1:2] -0.5 11 IN_OUT[3:7] -0.5 ...
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... Threshold above which POR is HIGH TH V Threshold above which POR is valid T 1. Corresponds to VCC supply voltage. Conditions 1 range, operating temperature, process. CC Conditions Controlled ramp setting FET turn off mode Conditions 4-5 ispPAC-POWR607 Data Sheet Min. Typ. Max 0.075 5.811 ±0.5 1.5 1 Min. Typ. ...
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... Lattice Semiconductor Figure 4-2. Internal Power-On Reset Reset State T BRO T RST T POR Start Up State T START Analog Calibration 4-6 ispPAC-POWR607 Data Sheet VCC POR (Internal) PLDCLK (Internal) VMONs Ready (Internal) ...
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... Figure 4-3. Power-Down Mode Timing VCC IN1_PWRDN (low = power-down) I (nominal) CC ICC Over Recommended Operating Conditions Conditions Device previously on T PWRDN_UP T PWRDN_HOLD I CC_PWRDN T PWRDN 4-7 ispPAC-POWR607 Data Sheet Min. Typ. Max. Units 12 48 240 250 260 kHz 0.032 1966 ms 13 -6.67 -12.5 100 100 300 ...
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... V = 3.3V supply 1 CCJ TDI, TMS, TCK 2.5V supply CCJ I = 10mA SINK I = 20mA SINK I = 4mA SINK I = 4mA SRC ; TDO, TDI, TMS, and TCK referenced to V 4-8 ispPAC-POWR607 Data Sheet Min. Typ. Max. +/- 0.8 0.7 2.0 1.7 0.8 0 CCJ Units µA µ ...
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... VIL State Update-IR Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH Run-Test/Idle (Program) Select-DR Scan 4-9 ispPAC-POWR607 Data Sheet Min. Typ. Max. 10 — — 30 — — 30 — — 200 — — — — 10 — — — — 10 — — 20 — ...
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... Theory of Operation Analog Monitor Inputs The ispPAC-POWR607 provides six independently programmable voltage monitor input circuits as shown in Figure 4-8. One programmable trip-point comparator is connected to each analog monitoring input. Each compara- tor reference has 192 programmable trip points over the range of 0.667V to 5.811V. Additionally, a 75mV ‘zero- detect’ ...
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... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. UTP LTP 4-11 ispPAC-POWR607 Data Sheet (a) (b) ...
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... Data Sheet 2.693 3.192 3.803 4.878 2.666 3.159 3.764 4.829 2.638 3.126 3.725 4.779 2.611 3.095 3.686 4.729 2.584 3 ...
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... CPLD. The PLD architecture allows flexibility in designing various state machines and control functions for power supply management. The AND array has 28 inputs and generates 81 product terms. The product terms are fed into a single logic block made macrocells. The output signals of the ispPAC-POWR607 device are derived from the PLD as shown in Figure 4-10. ...
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... Lattice Semiconductor Figure 4-10. ispPAC-POWR607 PLD Architecture VCC Sleep/ Wake Logic IN1_PWRDN IN2 5 IN_OUT[3:7] Output Feedback VMON[1: Timer0 Timer1 Timer2 Timer3 Macrocell Architecture The macrocell shown in Figure 4-11 is the heart of the PLD. The basic macrocell has five product terms that feed the OR gate and the fl ...
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... Polarity Clock Clock and Timer Functions Figure 4-12 shows a block diagram of the ispPAC-POWR607’s internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 4-12. Clock and Timer System Internal ...
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... IN1_PWRDN will always return the ispPAC-POWR607 to normal operation. Finally, whenever the ispPAC-POWR607 is in power-down mode, VCCJ is internally pulled to GND to turn off the JTAG I/O pins important, therefore, that the VCCJ pin be open when power-down mode is initiated. If connected to a power supply during power-down mode, VCCJ will draw approximately 2 ...
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... MCLK prior to going to the input AND array the same as the IN1 and IN2 digital inputs. High-Voltage Outputs The ispPAC-POWR607’s HVOUT1-HVOUT2 output pins can be programmed to operate either as high-voltage FET drivers or optionally as open drain digital outputs. Figure 4-14 shows the details of the HVOUT gate drivers. Each of these outputs is controlled from the PLD ...
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... Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispPAC-POWR607. A library of configurations is included with basic solu- tions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addi- tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 4-15, provides access to all confi ...
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... Figure 4-16. Download from a PC IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispPAC-POWR607 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispPAC-POWR607 as a serial programming interface. A brief description of the 2 CMOS memory of the ispPAC-POWR607. This con- ...
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... E CMOS cells these non-volatile cells that store the configuration or the ispPAC-POWR607. A set of instruc- tions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specifi ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR607 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver- ifi ...
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... BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC- POWR607. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). ...
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... OUTPUTS_HIGHZ. DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR607 for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. BULK_ERASE – This instruction will bulk erase all E POWR607 ...
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... PROGRAM_DONE_BIT – This instruction sets the ‘Done’ bit, which enables the ispPAC-POWR607 sequence to start. RESET – This instruction resets the PLD sequence and output macrocells. The condition of the ispPAC-POWR607 is the same as initial turn-on after POR is completed. PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the address register for the next read ...
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... FEATURE IS OPTIONAL. DIMENSION b APPLIES TO PLATED 4 TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. APPLIES TO EXPOSED PORTION OF TERMINALS 0. 0. 32X E B 0.50 TYP VIEW A VIEW A 4-25 ispPAC-POWR607 Data Sheet D2 PIN #1 ID FIDUCIAL LOCATED IN THIS AREA 0. BOTTOM VIEW SYMBOL MIN. NOM. ...
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... Use 32-pin QFNS package for all new designs. Refer to PCN #13A-08 for 32-pin QFN package discontinuance 4.75 5.00 L 32X 0. SYMBOL 4-26 ispPAC-POWR607 Data Sheet PIN #1 ID FIDUCIAL LOCATED IN THIS AREA DIEPAD (EXPOSED BACKSIDE 3.5 4X BOTTOM VIEW MIN. NOM. MAX. - 0.85 1.00 0.00 0.01 0.05 0.00 0.65 1.00 ...
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... Part Number ispPAC-POWR607-01S32I ispPAC-POWR607-01N32I 1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08. Lead-Free Packaging Part Number ispPAC-POWR607-01SN32I ispPAC-POWR607-01NN32I 1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08. Operating Temperature Range Package Performance Grade Industrial ...
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... Modified PLD Architecture figure to show input registers. Added 32-pin QFNS package Ordering Part Number information per PCN #13A-08. Updated ispPAC-POWR607 PLD Architecture diagram to clarify that the digital inputs are registered inputs to the AND array. Updated Digital Inputs and Optional Device Power Down text section. ...