AM29F017B Advanced Micro Devices, AM29F017B Datasheet - Page 12

• Manufacturer Part Number: AM29F017B
• Description: 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only/ Uniform Sector Flash Memory
• Manufacturer: Advanced Micro Devices

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
12
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
Figure 1. Temporary Sector Group Unprotect
once again.
Temporary Sector Group
Program Operations
Completed (Note 2)
Operation
Perform Erase or
RESET# = V
RESET# = V
Unprotect
(Note 1)
START
ID
IH
21195D-7
Am29F017B
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
IH
, the device does not ac-
. To initiate a write cycle,
IH
during power up, the
CC
power-up and
LKO
.
CC
CC