AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 143
AM79C973KCW
Manufacturer Part Number
AM79C973KCW
Description
PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C973KCW.pdf
(304 pages)
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CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31-16
15-0
CSR39: Next Next Transmit Descriptor Address
Uper
Bit
31-16
15-0
CSR40: Current Receive Byte Count
Bit
31-16
15-12
11-0
Name
RES
NNXDAL
Name
RES
NNXDAU
Name
RES
RES
CRBC
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next next transmit descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next next transmit descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
written as zeros.
This field is a copy of the BCNT
field of RMD1 of the current re-
ceive descriptor.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Reserved locations. Read and
Current Receive Byte Count.
P R E L I M I N A R Y
Am79C973/Am79C975
CSR41: Current Receive Status
Bit
31-16 RES
15-0
CSR42: Current Transmit Byte Count
Bit
31-16 RES
15-12 RES
11-0
CSR43: Current Transmit Status
Bit
31-16 RES
15-0
CSR44: Next Receive Byte Count
Bit
CXST
Name
CRST
Name
CXBC
Name
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Current Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the current transmit de-
scriptor.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Current Receive Status. This
field is a copy of bits 31-16 of
RMD1 of the current receive de-
scriptor.
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the current trans-
mit descriptor.
Description
Description
143
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