AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 299
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AM79C973KCW
Manufacturer Part Number
AM79C973KCW
Description
PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C973KCW.pdf
(304 pages)
- Current page: 299 of 304
- Download datasheet (3Mb)
External Address Reject Low . . . . . . . . . . .36
External Clock . . . . . . . . . . . . . . . . . . . . . .231
F
Far End Fault Generation and Detection . . .84
FIFO Burst Write At End Of
FIFO Burst Write At Start Of
FIFO DMA Transfers . . . . . . . . . . . . . . . . .60
Flash Read from Expansion Bus
Flash Write from Expansion Bus
Flash/EPROM Read . . . . . . . . . . . . . . . . . . .93
Flow, LAPP . . . . . . . . . . . . . . . . . . . . . . . .285
FMDC Values . . . . . . . . . . . . . . . . . . . . . .185
FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Frame Format at the MII Interface
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Full-Duplex Link Status LED Support . . . .79
Full-Duplex Operation . . . . . . . . . . . . . . . . .78
G
GENERAL DESCRIPTION . . . . . . . . . . . . .2
GNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
H
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . .107
I
I/O Buffer Ground (17 Pins) . . . . . . . . . . . .38
I/O Map In DWord I/O Mode
I/O Map In Word I/O Mode
I/O Registers . . . . . . . . . . . . . . . . . . . . . . .109
I/O Resources . . . . . . . . . . . . . . . . . . . . . . .109
IDSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
IEEE 1149.1 (1990) Test Access Port
IEEE 1149.1 Supported Instruction
IEEE 802.3 Frame And Length Field
Initialization . . . . . . . . . . . . . . . . . . . . . . . . .63
Initialization Block . . . . . . . . . . . . . . . . . .203
Initialization Block (SSIZE32 = 0) . . . . . .203
Unaligned Buffer . . . . . . . . . . . . . . . . . . .63
Unaligned Buffer . . . . . . . . . . . . . . . . . . .62
Data Port . . . . . . . . . . . . . . . . . . . . . . . . . .94
Data Port . . . . . . . . . . . . . . . . . . . . . . . . . .95
Connection . . . . . . . . . . . . . . . . . . . . . . .270
(DWIO = 1) . . . . . . . . . . . . . . . . . . . . . . .111
(DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . .110
Interface . . . . . . . . . . . . . . . . . . . . . .36, 106
Summary . . . . . . . . . . . . . . . . . . . . . . . . .106
Transmission Order . . . . . . . . . . . . . . . . . .77
P R E L I M I N A R Y
Am79C973/Am79C975
Initialization Block (SSIZE32 = 1) . . . . . .204
Initialization Block DMA Transfers . . . . . .56
Initialization Block Read In
Initialization Block Read In
Initialization Device Select . . . . . . . . . . . . .29
Initiator Ready . . . . . . . . . . . . . . . . . . . . . . .30
Input Setup and Hold Timing . . . . . . . . . .236
Instruction Register and Decoding
INTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Interface Pin Assignment . . . . . . . . . . . . . .177
Internal Loopback Paths . . . . . . . . . . . . . . .80
Internal SRAM Configuration . . . . . . . . . . .96
Interrupt Request . . . . . . . . . . . . . . . . . . . . .30
Introduction . . . . . . . . . . . . . . . . . . . . . . . .284
IRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IREF Internal Current Reference . . . . . . . . .37
J
Jabber Function . . . . . . . . . . . . . . . . . . . . . .87
JTAG (IEEE 1149.1) TCK Waveform
JTAG (IEEE 1149.1) Test Signal
K
Key to Switching Waveforms . . . . . . . . . .234
L
LAPP 3 Buffer Grouping . . . . . . . . . . . . . .288
LAPP Timeline . . . . . . . . . . . . . . . . . . . . .287
LAPP Timeline for Two-Interrupt
Late Collision . . . . . . . . . . . . . . . . . . . . . . . .75
LED Control Logic . . . . . . . . . . . . . . . . . .102
LED Default Configuration . . . . . . . . . . . .102
LED Support . . . . . . . . . . . . . . . . . . . . . . . .99
LED0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
LED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Legal I/O Accesses in Double
Legal I/O Accesses in Word I/O Mode
Link Change Detect . . . . . . . . . . . . . . . . . .103
Link Monitor . . . . . . . . . . . . . . . . . . . . . . . .84
Burst Mode . . . . . . . . . . . . . . . . . . . . . . . .57
Non-Burst Mode . . . . . . . . . . . . . . . . . . . .57
Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
for 5 V Signalin . . . . . . . . . . . . . . . . . . .238
Timing . . . . . . . . . . . . . . . . . . . . . . .228, 239
Method . . . . . . . . . . . . . . . . . . . . . . . . . .292
Word I/O Mode (DWIO =1) . . . . . . . . . .111
(DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . .111
299
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