TXC-02050C Transwitch, TXC-02050C Datasheet - Page 4

• Manufacturer Part Number: TXC-02050C
• Description: Line Interface
• Manufacturer: Transwitch

Proprietary TranSwitch Corporation Information for use Solely by its Customers
MRT
DATA SHEET
TXC-02050C
BLOCK DIAGRAM DESCRIPTION
On the Line Side, a symmetrical bipolar signal is applied to the input signal pin (DI1), which requires an exter-
nal 75 termination. DI2 is a DC reference voltage output which serves as an AC ground.
Equalization for various lengths of cable having a f attenuation characteristic is compensated by setting the
states of the EQB0 and EQB1 signal leads. The Equalization Network Block is connected to an AGC Block
which has approximately a 20 dB dynamic range. The AGC has separate voltage and ground leads for noise
immunity, and uses an external capacitor as part of an AGC filter. The AGC output is connected to the Clock
Recovery Block.
The Clock Recovery Block contains a phase-locked loop and supporting logic to generate a clock signal from
the line signal. The signal lead LOW selects the appropriate circuit in the Clock Recovery Block for the operat-
ing frequency and provides input attenuation for the receive line signal. The line input is monitored for loss of
signal, with an alarm indication provided on the RXLOS signal lead. The Clock Recovery Block requires an
external reference clock at the operating frequency (DCK). The reference clock is also used for generating and
sending a receive Alarm Indication Signal (AIS). The generation and sending of AIS for recovered data is con-
trolled by the RXAIS signal lead.
The output of the Clock Recovery Block is connected to the HDB3 Decoder Block, when enabled, or directly to
the I/O Circuits Block. When the decoder is enabled, indications of coding violation errors, other than the nor-
mal HDB3 zero substitution codes, are provided as pulses on the signal lead labeled CV by the CV Detector
and LQ Indicator Block. Examples of HDB3 coding and violations are shown in Figure 19. An external clock
-6
(BERCK) is used to generate a 10-second sampling window for detecting a 10
or greater error rate. The
resulting line quality indication is provided on the output signal lead LQLTY.
Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface. The
selection is determined by the state placed on the input signal lead PNENB. When a low is applied to this sig-
nal lead, the HDB3 Decoder and HDB3 Encoder Blocks are bypassed, and the terminal side I/O is a positive
and negative rail interface. When a high is applied to the signal lead, an NRZ interface is provided. Data is
clocked out of the MRT on negative edges of the clock output signal (CLKO). Receive data and the clock sig-
nals are disabled, and forced to a high impedance state, by placing a low on the receive disable input lead
(RXDIS). For a receive positive and negative rail interface, an inverted clock output signal (CLKO) is also pro-
vided.
The terminal side interface for the transmitter can either be positive and negative rail (TP and TN) or NRZ (TD)
data depending on the state of the common control input lead PNENB (see Figure 20 for examples). Data is
clocked into the MRT on positive transitions of the clock signal (CLKI). The input clock is monitored for the loss
of clock. When the input clock remains high or low, TXLOC will be set low. The MRT also provides the capabil-
ity to generate and insert AIS (all ones signal), independent of the transmit data. A low placed on the TXAIS
input lead enables the transmit AIS generator.
Two loopbacks are provided, transmit loopback and receive loopback. Transmit loopback connects the data
path from the transmitter Output Driver Block to the Clock Recovery Block, and disables the external receiver
input. Transmit loopback is activated by placing a low on the LBKTX input signal lead. Receive loopback con-
nects the receive data path to the transmit output circuits and disables the transmit input. Receive loopback is
activated by placing a low on the LBKRX input signal lead.
For 6 Mbit/s operation, the MRT should be operated in the P and N rail mode, bypassing the HDB3 Decoder/
Encoder. When the MRT is used with the TranSwitch JT2F device at this bit rate, the JT2F can provide either
B6ZS or B8ZS encoding and decoding.
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TXC-02050C-MB
Ed. 1, May 2002