TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet
TXC-04252AIPQ
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TXC-04252AIPQ Summary of contents
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... U.S. Patents No. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057; 5,297,180; 5,473,611; 5,528,598; 5,535,218; U.S. and/or foreign patents issued or pending Copyright 2000 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DESCRIPTION The Quad E1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single uni- directional ring applications ...
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... Start-Up Procedure .................................................................................................................. 73 Pointer Leak Rate Calculations ................................................................................................ 74 Jitter Measurements ................................................................................................................. 75 Internal Spot Processor ............................................................................................................ 80 Boundary Scan ......................................................................................................................... 84 Multiplex Format and Mapping Information .............................................................................. 93 Memory Map ................................................................................................................................... 99 Memory Map Descriptions ............................................................................................................. 105 Package Information ..................................................................................................................... 138 Ordering Information ..................................................................................................................... 140 TXC-04252-MB Ed. 3, December 2000 DATA SHEET TABLE OF CONTENTS - 2 of 148 - Page ...
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... QE1M TXC-04252 Block Diagram......................................................................................... 4 2. 2048 kbit/s Asynchronous Mapping....................................................................................... 8 3. QE1M TXC-04252 Plastic Quad Flat Package Lead Diagram .............................................. 9 4. QE1M TXC-04252 Plastic Ball Grid Array Package Lead Diagram..................................... 10 5. Ports and 4 E1 Transmit Timing ............................................................................... 25 6. Ports and 4 E1 Receive Timing ................................................................................ 26 7. ...
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... B Transmit TU/VT Build (B Add) B Side 11 TCK TMS IEEE 1149.1 Boundary TDI Scan Input/Output TDO TRS Figure 1. QE1M TXC-04252 Block Diagram TXC-04252-MB Ed. 3, December 2000 DATA SHEET Repeated for Ports and 4 HDB3 Destuff Desync Coder Alarms & Controls Stuff/Sync A Side Stuff/Sync B Side ...
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... SDH/SONET AIS indication. The Quad E1 Mapper can monitor either the TOH E1 bytes or the H1/H2 bytes for an AIS indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected. DATA SHEET bus timing, the add buses are, by definition, byte- and multiframe-syn 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, a parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The Add C1J1V1 signal is used in conjunction with the Add SPE signal to determine the location of the various pulses. An option is pro- TXC-04252-MB Ed. 3, December 2000 DATA SHEET ...
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... The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external Input/Output leads from the TAP for board and component test. DATA SHEET - 7 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... REI = Remote Error Indication (formerly FEBE, Far End Block Error Indication) RFI = Remote Failure Indication Signal Label RDI = Remote Defect Indication (formerly FERF, Far End Receive Failure Indication) Figure 2. 2048 kbit/s Asynchronous Mapping TXC-04252-MB Ed. 3, December 2000 DATA SHEET VC- bytes (2048 kbit/s Data ...
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... UPA8 (A8) UPA9 (A9) Note: See Figure 28 for Package Information. X(Y/Z) format is used for microprocessor interface signals to identify Multiplex (Intel/Motorola) interface functions, where these are different. Figure 3. QE1M TXC-04252 Plastic Quad Flat Package Lead Diagram DATA SHEET QE1M Lead Diagram (Top View) TXC-04252 ...
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... This is the bottom view. The leads are solder balls. See Figure 29 for package information. Some signal Symbols have been abbreviated to fit the space available. The Symbols are shown in full in the Lead Descriptions section. Figure 4. QE1M TXC-04252 Plastic Ball Grid Array Package Lead Diagram TXC-04252-MB Ed. 3, December 2000 ...
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... VDD: +5 volt supply voltage, 5%. P Ground: 0 volt reference. No Connect: NC leads are not to be connected, not even to another NC lead, but must be left floating. Con- nection of these leads may impair performance or cause damage to the device 148 - QE1M TXC-04252 Name/Function TXC-04252-MB Ed. 3, December 2000 ...
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... M3 ADC1J1V1 ADIND *See Input, Output and Input/Output Parameters section below for Type definitions. TXC-04252-MB Ed. 3, December 2000 DATA SHEET I/O/P Type * I TTL A Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 opera- tion. A Drop bus byte-wide data (AD7-AD0), the parity bit ...
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... A Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDI is 1, the indica- tor is active high instead of active low 148 - QE1M TXC-04252 Name/Function TXC-04252-MB Ed. 3, December 2000 ...
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... BDSPE 93 L15 BDC1J1V1 94 L16 101 J14 BDIND TXC-04252-MB Ed. 3, December 2000 DATA SHEET I/O/P Type I TTL B Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 opera- tion. B Drop bus byte-wide data (BD7-BD0), the parity bit ...
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... B Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDI is 1, the indica- tor is active high instead of active low 148 - QE1M TXC-04252 Name/Function TXC-04252-MB Ed. 3, December 2000 ...
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... MICROPROCESSOR BUS INTERFACE SELECTION Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. MUX 3 C1 TXC-04252-MB Ed. 3, December 2000 DATA SHEET I/O/P Type O(T) CMOS Receive Port n Output Clock: A 2.048 MHz clock out- 4mA put. Data is normally clocked out on rising edges of this clock. When control bit RCKI is 1, data is clocked out on falling edges of this clock ...
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... Interrupt: A high or low on this output lead signals 8mA an interrupt request to the microprocessor. The polarity of this signal is determined by the state of the INTSH lead 148 - QE1M TXC-04252 Name/Function Action Multiplex bus interface Intel bus interface Motorola bus interface Name/Function TXC-04252-MB Ed. 3, December 2000 ...
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... B8 SEL 147 RD/WR 148 LDS TXC-04252-MB Ed. 3, December 2000 DATA SHEET I/O/P Type I TTL Interrupt Sense High Selection: A high on this lead causes the interrupt sense to be high when an interrupt occurs. A low causes the interrupt sense to be low when an interrupt occurs. ...
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... FIFOs and internal SPOT pro- cessor. The microprocessor must write the control bit states for normal operation 148 - QE1M TXC-04252 Name/Function Name/Function . It must be left floating or held DD TXC-04252-MB Ed. 3, December 2000 ...
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... TMS 36 N2 TDI 38 R1 TDO TRS TXC-04252-MB Ed. 3, December 2000 DATA SHEET I/O/P Type I TTL High Impedance Select: A low forces all output leads to the high impedance state for testing purposes (except TDO). I TTL Add Bus Timing Select: A low selects the A and B Add bus clock, SPE and C1J1V1 input signals for deriving tim- ing for the A and B Add buses ...
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... Note 1 + 0.5 V Note Note ft/min linear airflow Level per EIA/JEDEC JESD22-A112-A % Note 2 % non-condensing V Note 3 JEDEC STD-17 Unit Test Conditions o C/W 0 ft/min linear airflow o C/W 0 ft/min linear airflow Unit Test Conditions V mA STS-1 mW STS-1 mA STM-1 or STS-3 mW STM-1 or STS-3 TXC-04252-MB Ed. 3, December 2000 ...
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... V 0 Input capacitance Input Parameters For TTL Parameter Input capacitance Input Parameters For TTLp Parameter Input capacitance Input Resistance TXC-04252-MB Ed. 3, December 2000 DATA SHEET Min Typ Max DD 0 7.5 Min Typ Max 2.0 0.8 7.5 Min Typ Max 2.0 0.8 7 ...
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... Min Typ Max 2.4 0.4 4.0 -4.0 7.5 Min Typ Max 2.4 0.4 8.0 -8.0 7 148 - QE1M TXC-04252 Unit Test Conditions 4.75 -4 4.75 4 Unit Test Conditions 4.75 -4 4.75 4 Unit Test Conditions 4.75 -8 4.75 8 TXC-04252-MB Ed. 3, December 2000 ...
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... IL Input capacitance Input capacitance Input/output Parameters For TTL 8mA Parameter Input capacitance TXC-04252-MB Ed. 3, December 2000 DATA SHEET Min Typ Max 2.0 0.8 5.5 2.4 0.4 4.0 -4.0 7.5 Min Typ Max 2.0 0.8 2.4 0.4 8.0 -8.0 7 148 - Unit Test Conditions V 4 ...
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... TCIn clock high time TPIn/TNIn data setup time before TCIn TPIn/TNIn data hold time after TCIn DATA SHEET t CYC t t PWH PWL Symbol Min Typ t 488.28 CYC t 150 PWL t 150 PWH 2 148 - QE1M TXC-04252 + V )/2 for input sig Max Unit TXC-04252-MB Ed. 3, December 2000 ...
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... RCOn clock low time (RCLKI = 0) RCOn clock high time (RCLKI = 0) RCOn clock low time (RCLKI = 1) RCOn clock high time (RCLKI = 1) RPOn/RNOn data delay after RCOn Note: All output times are measured with a maximum 75 pF load capacitance. TXC-04252-MB Ed. 3, December 2000 DATA SHEET t CYC t ...
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... Occurs every four frames when provided in place of the H4 byte J1 V1 Drop Bus TU/VT Time Slot when enabled t OD(3) TU/VT Selected Add Bus TU/VT Time Slot when enabled Min Typ Max Unit 154 5 7.0 9.0 ns TXC-04252-MB Ed. 3, December 2000 ...
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... ADD add indicator delay from DCLK AIND add bus indication output delay from DCLK A(7-0)/APAR data /parity out tristate to driven delay from DCLK Note: All output times are measured with the specified load capacitance. TXC-04252-MB Ed. 3, December 2000 DATA SHEET TU/VT J1 Byte ...
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... H(2) t OD(2) 75pF t OD(3) t OD(1) 25pF t OD(4) t 75pF OD( 148 - QE1M TXC-04252 Occurs every four frames when provided OD(3) TU/VT Selected Add Bus TU/VT Time Slot when enabled Min Typ Max Unit 154. 5 5 5.0 7.0 ns TXC-04252-MB Ed. 3, December 2000 ...
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... ADD add indicator delayed from ACLK AIND add bus indication output delay from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK Note: All output times are measured with the specified load capacitance. TXC-04252-MB Ed. 3, December 2000 DATA SHEET t H(2) ...
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... D(1) t PW(3) Symbol t PW(1) t SU(1) t H(1) t H(2) t OD(1) t W(1) t SU(2) t H(3) t W(2) t PW(2) t D(1) t D( 148 - QE1M TXC-04252 t W(1) t OD(1) t H(3) t F(1) tristate Min Typ Max Unit 20 ns 5.0 ns 3.0 ns 2 0.0 ns 0 TXC-04252-MB Ed. 3, December 2000 ...
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... Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, result- ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high SPcyc. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol ...
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... W(2) PW(2) t D(2) t D(1) t PW(3) Symbol Min t 20 PW(1) t 0.0 W(1) t 5.0 SU(1) t 3.0 H( SU(2) t 6.0 H(2) t 0.0 SU(3) t 0 PW(2) t 2.0 D(1) t 4.0 D(2) t 2.0 F( 148 - QE1M TXC-04252 t H(2) H(3) t F(1) Typ Max Unit TXC-04252-MB Ed. 3, December 2000 ...
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... Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, result- ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high SPcyc. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol ...
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... DATA SHEET Address t D(5) Data t D(1) t SU(2) t PW(1) t D(3) t D(4) t D(2) t PW(2) Symbol Min t 0.0 SU(1) t 3.0 H(1) t 2.0 F( SU( PW(1) t 0.0 H(2) t 2.0 D(2) t 4.0 D(3) t 2.0 F( 148 - QE1M TXC-04252 t H(1) t F(1) t H(2) t F(2) Typ Max Unit TXC-04252-MB Ed. 3, December 2000 ...
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... Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, result- ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high SPcyc. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol ...
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... H(1) Address t H(2) Data t SU(2) t SU(4) t SU(3) t PW(1) t D(2) t PW(2) Symbol Min t 0.0 SU(1) t 3.0 H( SU(2) t 6.0 H( SU( PW(1) t 2.0 D(1) t 4.0 D( PW( SPcyc 9 * SPcyc SPcyc SU( 148 - QE1M TXC-04252 t F Typ Max Unit 0 SPcyc SPcyc ns ns TXC-04252-MB Ed. 3, December 2000 ...
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... Data RAM read (Note 3) D(7-0) data output delay Register read only after CS D(7-0) data output delay SPOT instruction read and data after DTACK RAM read only D(7-0) data output tristate to drive delay after CS TXC-04252-MB Ed. 3, December 2000 DATA SHEET Address t D(1) t D(5) Data ...
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... Maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction read or data RAM read cycle, DTACK stays high after t DTACK settles to low after t . DTACK may go directly from a low to a high impedance state. ) D(3 DATA SHEET . During a register read cycle, D( 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... DTACK stable delay after address becomes stable (Note 4) Register write DTACK pulse width SPOT instruction write (Note 2) Data RAM write (Note 3) D(7-0) data valid setup SPOT instruction write and data time to CS RAM write only TXC-04252-MB Ed. 3, December 2000 DATA SHEET Address t SU(2) Data t SU(3) t ...
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... Maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction write or data RAM write cycle, DTACK stays high after t DTACK settles to low after t DTACK may go directly from a low to a high impedance state. D(3 ). DATA SHEET . During a register write cycle, D( 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay from TCK (Note 1) TRS Pulse Width Note 1: The output time (TDO) is measured with a maximum load capacitance. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Figure 17. Boundary Scan Timing PWH t ...
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... In the dual unidirectional ring mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path both the A and B Add buses. Timing for the TU/ added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. DATA SHEET - 43 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... The control bit settings for format selection are given in the table shown below. When the STS-1 format is selected, the buses are configured to operate at a bus rate of 6.48 Mbyte/s, instead of 19.44 Mbyte/s for VC-4/AU-3/STS-3 formats. STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format TXC-04252-MB Ed. 3, December 2000 DATA SHEET TnSEL0 RnSEL 0 0 ...
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... STS-1 AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 No TU/VT Selected TU/VT Number 1 TU/VT Number 2 TU/VT Number 3 TXC-04252-MB Ed. 3, December 2000 ...
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... The TU-12 (VT2) number selection register labels (TTUNn), which consist of seven bits, are given in the follow- ing table. An out of range value forces a high impedance state on the add bus. Locations 04DH (port 1), 07DH (port 2), 0ADH (port 3), 0DDH (port 4) Bit AU-3/TUG-3 or TU/VT Group Number STS TXC-04252-MB Ed. 3, December 2000 DATA SHEET TU/VT Number ...
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... UEAME bit in register 014H. The following table describes these differ- ences. DATA SHEET DRPBT X Add bus timing selected by ABUST lead. X Drop bus timing selected by ABUST lead. 0 Add bus timing selected by DRPBT bit. 1 Drop bus timing selected by DRPBT bit. Bus Timing Selection - 47 of 148 - QE1M TXC-04252 Action TXC-04252-MB Ed. 3, December 2000 ...
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... Notes Don’t Care (0 or 1). 2. Only Multiplexed Mode is effected by the UEAME control bit. All other modes operate the same way regardless of the state of the UEAME control bit. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Unequipped Channel Generation Add/Drop Mode Drop From ...
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... BsDH4E) if two or more H4 byte values differ from those of a 2-bit counter for two consecutive mul- tiframes. Recovery occurs when four consecutive sequential H4 byte values are detected once. DATA SHEET 2048 kbit/s TU/VT H4 (XXXX XX00 Previous SPE 35 Bytes H4 (XXXX XX01 Bytes H4 (XXXX XX10 Bytes H4 (XXXX XX11 Bytes - 49 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... Add bus timing 1 selected Note Don’t Care. Bus timing mode is selected via lead ABUST and control bits SBTEN, DRPBT, as described earlier. Add and Drop Bus V1 Reference Selection TXC-04252-MB Ed. 3, December 2000 DATA SHEET DV1SEL 0 Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location, and added TU/VT V1 byte starting location ...
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... QE1M TXC-04252 RDIS TCUQ TCLL RDIP TCAIS TCTM RDIC TCLM TCODI TCRDI • • • • • • • • • • • • • TXC-04252-MB Ed. 3, December 2000 ...
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... In addition, the hardware and software interrupt may be released by writing the mask bits that correspond to the interrupt indication register. For AnAIS, the interrupt can be masked by writing 0 to PnMSK or to the RPTnA bits. TXC-04252-MB Ed. 3, December 2000 DATA SHEET - 52 of 148 - ...
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... RPT1A RPT1B TFIFO2B TFIFO1A TFIFO1B RFIFO3 RFIFO2 RFIFO1 A3UAISI A2UAISI A1UAISI A3DH4E A2DH4E A1DH4E B3UAISI B2UAISI B1UAISI B3DH4E B2DH4E B1DH4E AnRFI AnUNEQ AnSLER AnJ2TIM 0 0 AnTCODI AnTCRDI 0 BnRFI BnUNEQ BnSLER BnJ2TIM 0 0 BnTCODI BnTCRDI 0 TnLOS TnLOC TnDAIS TXC-04252-MB Ed. 3, December 2000 ...
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... PERR 0 B3DH4E B2DH4E B1DH4E Note 1. The SPOT alarm does not have an interrupt indication bit but it can still cause both software interrupt (INT bit) and hardware interrupt (INT/IRQ lead). TXC-04252-MB Ed. 3, December 2000 DATA SHEET Interrupt Mask Additional Interrupt Mask or (if any) ...
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... BnTCUQ 08C port 2 BnTCAIS 0BC port 3 BnTCLM 0EC port 4 BnTCLL BnTCTM BnTCODI BnTCRDI - 55 of 148 - QE1M TXC-04252 Additional Interrupt Interrupt Interrupt Indication Mask Mask Bit (021H) (if any) (020H) (017H) PnMSK RPTnB PORTn RFIE (Note 1) RPTnB TXC-04252-MB Ed. 3, December 2000 ...
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... Proprietary TranSwitch Corporation Information for use Solely by its Customers. QE1M TXC-04252 Latched Alarm Alarm Name Address 044 port 1 074 port 2 0A4 port 3 0D4 port 4 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Common Port n Alarms and Interrupts Additional Interrupt Mask Interrupt Mask (021H) (if any) (018H or 019H) ...
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... Alarm event register sets, and software inter- rupt indication occurs, on positive and/or neg- ative transitions of the alarm; no hardware interrupt Alarm event register sets, and software and hardware interrupt indications occur, on posi- tive and/or negative transitions of alarm 148 - QE1M TXC-04252 Action on an Alarm TXC-04252-MB Ed. 3, December 2000 ...
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... H1/ Byte AIS) is set. Recovery occurs when 4 or more zeros (at least 4 bits equal to 0 out of the 8 bits) are detected once. The E1n byte AIS detection circuits (when selected) for both the A and B Drop buses are disabled by writing control bit HEAISE. TXC-04252-MB Ed. 3, December 2000 DATA SHEET ...
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... The pointer offset arrangement for this format is shown below. DATA SHEET Pointer Bytes Bit Assignment 2048 kbit/s TU-12/VT2 V1 105 106-138 139 36- 71-103 104 TU/VT Pointer Offset Locations - 59 of 148 - QE1M TXC-04252 V2 Byte TXC-04252-MB Ed. 3, December 2000 ...
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... AIS to LOP is disabled (shown dotted), which is required in Bellcore recommendations. INC NDF_enable (Accept New Offset) NDF_enable (Accept New Offset) NDF 8 x NDF_enable (Offset Undefined) Figure 19. TU/VT Pointer Tracking State Machine TXC-04252-MB Ed. 3, December 2000 DATA SHEET 3 x AIS_ind (Offset Undefined) inc_ind (Incr. Offset any_point 3 x new_point (Accept New Offset) ...
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... Remote Server Defect - VT Loss of Pointer - VT AIS detected - Upstream AIS detected (E1 or H1/H2 Bytes). 0 Remote Connectivity Defect - Unequipped Signal Label - J2 Mismatch - J2 Loss of Lock 1 Remote defect (old equipment). RDI Bit Assignment for 3-Bit RDI - 61 of 148 - QE1M TXC-04252 Definition TXC-04252-MB Ed. 3, December 2000 ...
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... The priority used for sending RDI if more than one of the microprocessor controls are set is: Server, Connectivity, and Payload. When RDIEN = 1 and no defects are gen- erated then K4 bits 5,6,7 = 001. TXC-04252-MB Ed. 3, December 2000 DATA SHEET ...
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... Microprocessor writes T1RDIS to generate a Remote Defect Indication. DATA SHEET defect indications Remote Defect Indication. RDI Bit Assignment for 1-Bit RDI AnRDIS BnRDIS 0 No defect indications. 1 Remote Defect Indication. RDI Alarm Definition for 1-Bit RDI - 63 of 148 - QE1M TXC-04252 Definition Action TXC-04252-MB Ed. 3, December 2000 ...
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... OOOO RR) in the first justification control byte, and bits 7 through O-bit register corre- spond to bits 3 through 6 in the second justification control byte, as shown below. Second Justification Control Byte Bit 3 Register 7 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Other Bytes J2 Byte C2 ...
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... Transmit and receive J2 segments are configured for the 64-byte J2 message size. Microprocessor read for the dropped J2 mes- sage. J2 alarms are disabled. The tandem connection feature must be disabled by setting TCnEN=0 for the port 16-Byte J2 Message ITU-T 16-Byte J2 Message Format - 65 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... Loss of Lock (J2nLOL = 1) when AcTI messages - J2 Trace Identifier Mismatch (J2nTIM comparison between the Received stable message (AcTI) and the microprocessor-written reference message (ExTI). - Declare Mismatch (J2nTIM = 1) when AcTI TXC-04252-MB Ed. 3, December 2000 DATA SHEET E1Mx16 Definitions Incoming J2 trace message (Real Time) Microprocessor-written trace (reference) message ...
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... X40=0x00). The Loss of Lock alarm will set, and then the re-start the algorithm from the beginning, which resets the mismatch alarm, and starts searching again for the alignment pattern. DATA SHEET - 67 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... TC Trace ID Byte No C7 Trace ID Byte No Trace ID Byte No thru Trace ID Bytes No. 3 thru Trace ID Byte No Trace ID Byte No Bit Bit RDI 74 Bit ODI, Bit Bit Bit Bit Bit TXC-04252-MB Ed. 3, December 2000 DATA SHEET AIS TC 1 Indication REI N2 (Z6) Byte Definition - 68 of 148 - OEI Trace ID ...
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... N2 (Z6) bytes are not equal to XX00 0000. Note that bits 1 and 2 of the N2 (Z6) byte are masked (shown as X) and do not affect the indication. DATA SHEET - 69 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... TUG-3 are tristated on the add bus. When written to control bit NULLZ in address 013H, bit 3 and the NPI feature is enabled (i.e., NPIA, NPIB or NPIC the bytes following the NPI bytes are transmitted as zeros. When the NULLZ bit the bytes following the NPI bytes are tristated. TXC-04252-MB Ed. 3, December 2000 DATA SHEET ...
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... NRC 0 ANAnOOL 1 HDB3 Coder Facility Loopback XMIT NRZ HDB3 0 NRZ Coder NRZ 1 BYPASn Clock - 71 of 148 - QE1M TXC-04252 BYPASn NRZ 1 Receive Data & Clock Rail (NRZ, Rail) 0 Line E1 LINE Loopback 1 Transmit 0 Data & Clock (NRZ, Rail) LnLBK TXC-04252-MB Ed. 3, December 2000 ...
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... SPOT alarms (i.e., addresses 026H to 028H). Note that a hardware reset will automatically trigger all the software reset bits. Software reset bit RESET will trigger all RnSETS, all RnSETC, RESTAB and RESTBB automatically. A RnSETS will also automatically trig- ger a RnSETC. TXC-04252-MB Ed. 3, December 2000 DATA SHEET 15 -1 PRBS patterns, as illustrated in 20 ...
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... Clear A2LOP (read register 0x060) - Clear A3LOP (read register 0x090) - Clear A4LOP (read register 0x0C0) - Clear B1LOP (read register 0x03A) - Clear B2LOP (read register 0x06A) - Clear B3LOP (read register 0x09A) - Clear B4LOP (read register 0x0CA) DATA SHEET - 73 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
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... Recalculate the value of 'C' by subtracting the oldest sample and adding the newest, and calculate a new leak rate, as described in Note 5 (e.g., using S2 through S11). 8. Continue to repeat the steps described in Notes 5, 6 and 7 until AIS, LOP, LOS or NDF is received or until you reset the QE1M. TXC-04252-MB Ed. 3, December 2000 DATA SHEET 10 SEC ...
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... DATA SHEET Filter Characteristics f1 f3 (High Pass) (High Pass kHz 20 dB/decade 20 dB/decade -20 dB/decade HP1 HP2 Requirement Maximum Input Jitter Tolerated (UI-PP) >1 > 1.5 UI 2.3 UI > 0.2 UI 2.2 UI > 0 148 - QE1M TXC-04252 f4 (Low Pass) 100 kHz LP TXC-04252-MB Ed. 3, December 2000 ...
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... Figure 21. Jitter Tolerance and Jitter Test Arrangements External QE1M Loopback Test Fixture 155 Mbit/s Figure 22. Jitter Tolerance Measurements 10 1 0.1 10 100 Input Jitter Frequency, Hz TXC-04252-MB Ed. 3, December 2000 DATA SHEET Receiver 2.048 Mbit/s E1 Interface Transmitter JITTER TOLERANCE 1000 10000 - 76 of 148 - PDH Digital ...
Page 77
... DATA SHEET Filter Used Unit Interval 1.0 UI f1-f4 (HP1/LP) 1.0 UI 1.0 UI 1.0 UI 1.0 UI 1.0 UI 100 Input Jitte r Fre que ncy - 77 of 148 - QE1M TXC-04252 Jitter Transfer (UI - PP, max) 0.172 UI 0.127 UI 0.117 UI 0.099 UI 0.076 UI 0.075 UI Input ured 1000 TXC-04252-MB Ed. 3, December 2000 ...
Page 78
... Note 2: The limit corresponds to the pointer sequences shown in Figure 24 for Standard Pointer Test Sequences, ( > 0. ms). The T3 value was constrained by test equipment limitations. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Filter Characteristics Maximum Output Jitter (UI-PP) ...
Page 79
... Proprietary TranSwitch Corporation Information for use Solely by its Customers. Figure 24. Standard Pointer Test Sequences Single Pointers of Opposite Polarity T2 Regular Pointers plus one Double Poiner T2 Regular Pointers with one Missing Value T3 Double Pointers of Opposite Polarity DATA SHEET (Ref: ITU-T G.783, Fig. 6- 148 - QE1M TXC-04252 T3 TXC-04252-MB Ed. 3, December 2000 ...
Page 80
... Watchdog Timer Expired (WDTEXP) in bit 6 of addresses 028H and 029H indicates that the SPOT processor may be unable to service all requests in a timely manner. Some possible causes for this condition are excessive microprocessor accesses, a SPOT processor clock that is running too slowly software bug. TXC-04252-MB Ed. 3, December 2000 DATA SHEET - 80 of 148 - ...
Page 81
... RAM and reset its general purpose registers to allow other subroutines to begin running from a known state. DATA SHEET Microprocessor Description Interface Address 102H IRAMptr <== SPOTPCLD(10-0) 102H read IRAMptr[7:0] 103H read IRAMptr[10:8] 100H *IRAMptr++ <== data 100H data <== *IRAMptr 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 82
... QE1M TXC-04252 Figure 25. Schematic Diagram of QE1M Showing SPOT Processor Interfaces SDH/SONET SIDE Drop[A] Drop[B] Inst. Data RAM RAM Add[A] Add[B] TXC-04252-MB Ed. 3, December 2000 DATA SHEET DROP Engine RAM I/F Control/Status P Interface SPOT ADD Engine - 82 of 148 - LINE SIDE Rx Port P Input/Output ...
Page 83
... Note: RESTSP must be 0 during reprogramming. DATA SHEET Initialize LATEN = 0 HDWIE = 1 SPTMSK = 1 SPOTPCLD=000H RPSPOT = 1 wrPC 102H = 00H Write next byte No more data? n 100H = data y wrPC 102H = 00H Read next byte No more data? n data = 100H y Wrap Up RPSPOT = 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 84
... V Output and Input/Output Parameters’ section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor. TXC-04252-MB Ed. 3, December 2000 DATA SHEET - 84 of 148 - requirements listed in the ‘ ...
Page 85
... Instruction Register Bypass Register TAP Controller 3 TDI Controls IN Boundary Scan Serial Test Data DATA SHEET TDO OUT - 85 of 148 - QE1M TXC-04252 Signal input and output leads (shown for PQFP; PBGA package has solder ball leads on bottom surface). TXC-04252-MB Ed. 3, December 2000 ...
Page 86
... Output (3-state Output (3-state --- --- 15 Output (3-state --- --- 17 Output (3-state Output (3-state --- --- 20 Output (3-state --- --- 22 Input 8 23 Input 7 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol PBGA P1 TDO SCAN Chain output M3 ADSPE L2 ADC1J1V1 L1 AASPE L4 AAC1J1V1 K2 AACLK K3 ADCLK J2 ADIND J3 AAIND H1 TPI1 G4 TNI1 G1 TCI1 G2 QUIET1 F4 RPO1 F3 RNO1 RN1_OE When high, lead tristated ...
Page 87
... ABUST UPA_OE2 When high, leads 158 or A3, 159 or A2, 160 or B2 and are tristated (in (out) C5 RESET C6 A5 (in (out) D6 INT/IRQ INT_OE When high, lead 152 tristated. B7 INTSH A7 ALE Used only in MUX mode (WR/LDS (RD / RD/WR 148 - QE1M TXC-04252 Comments TXC-04252-MB Ed. 3, December 2000 ...
Page 88
... Output (3-state) 133 70 Input 132 71 Output (3-state) 132 72 Input 130 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol PBGA UPA_OE1 When high, leads 144 or C8, 153 or C6 and 156 or B5 are tristated. B8 SEL UPA_OE0 When high, leads 135 or B10, 140 or B9, 141 or C9 and 143 or D8 are tristated. ...
Page 89
... UPD_OE0 When high, leads 124 or B13 and 125 or C13 are tristated. B15 QUIET4 A16 TCI4 C15 TNI4 C16 TPI4 D14 RCO4 E15 RNO4 RN4_OE When high, lead 113 or E15 is tristated. E14 RPO4 - 89 of 148 - QE1M TXC-04252 Comments TXC-04252-MB Ed. 3, December 2000 ...
Page 90
... Input 83 122 Input 82 123 Input 80 124 Output (2-state) 78 125 Output (3-state) 77 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol PBGA RCP4_OE When high, leads 112 or E14 and 114 or D14 are tristated. E13 RCO2 F16 RNO2 RN2_OE When high, lead 110 or F16 is tristated. ...
Page 91
... T10 are tristated. N10 AA2 R9 AA3 N9 AA4 AA_OE1 When high, leads and are tristated. N8 AA5 P8 AA6 P7 AA7 T7 AAPAR AA_OE2 When high, leads and tristated. R7 AADD N6 AD0 P6 AD1 T6 AD2 - 91 of 148 - QE1M TXC-04252 Comments TXC-04252-MB Ed. 3, December 2000 ...
Page 92
... QE1M TXC-04252 Scan I/O Lead No. Cell No. PQFP 153 Input 48 154 Input 47 155 Input 46 156 Input 44 157 Input 43 158 Input 42 Input 38 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Symbol PBGA N5 AD3 P5 AD4 T5 AD5 P4 AD6 R4 AD7 T3 ADPAR R1 TDI SCAN chain input - 92 of 148 - Comments ...
Page 93
... MULTIPLEX FORMAT AND MAPPING INFORMATION STS-1 VT2 (2.048 Mbit/s) Multiplex Format Mapping The following diagram and table illustrate the mapping of the 21 VT2s into an STS-1 SPE. Column 1 is assigned to carry the path overhead bytes. VT2 4 COLUMNS DATA SHEET 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 94
... QE1M TXC-04252 RTUNn, TTUNn Locations VT# 04CH, 04DH Port 1 0ACH, 0ADH Port 3 07CH, 07DH Port 2 0DCH, 0DDH Port Note: Columns 30 and 59 carry fixed stuff bytes. Column 1 is assigned for the POH bytes. TXC-04252-MB Ed. 3, December 2000 DATA SHEET STS-1 Mapping (2.048 Mbit/ ...
Page 95
... The following diagram and table illustrate the mapping of the 63 VT2/TU-12s into an STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes. VT2 4 COLUMNS BYTES Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff. DATA SHEET STS-3/AU-3 SPE - 95 of 148 - QE1M TXC-04252 261 TXC-04252-MB Ed. 3, December 2000 ...
Page 96
... STS-1 #1, AU Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff. TXC-04252-MB Ed. 3, December 2000 DATA SHEET STS-3/AU-3 Mapping (2.048 Mbit/s) RTUNn, TTUNn 04CH, 04DH Port 1 TU/ 07CH, 07DH Port 2 STS-3/AU-3 VT 0ACH, 0ADH Port 3 ...
Page 97
... The following diagram and table illustrate the mapping of the 63 TU-12s into an STM-1/VC-4. The QE1M pro- vides control bits for enabling the Null Pointer Indicators (NPIs) for the columns indicated. 4 COLUMNS TUG VC DATA SHEET 4 TU- TUG-3A TUG-3B STM-1/VC 148 - QE1M TXC-04252 TUG-3C 261 TXC-04252-MB Ed. 3, December 2000 ...
Page 98
... TXC-04252-MB Ed. 3, December 2000 DATA SHEET STM-1 VC-4 Mode (2048 kbit/s) RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 VC-4 TU 0ACH, 0ADH Port 3 Column # 0DCH, 0DDH Port 4 Numbers Registers ...
Page 99
... Part 2 of two-part program release number (PGMRV2) * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. DATA SHEET Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit 148 - QE1M TXC-04252 Bit 2 Bit 1 Bit Growth (reads as 0000) Bit 2 Bit 1 Bit 0 TXC-04252-MB Ed. 3, December 2000 ...
Page 100
... TFIFO4A TFIFO4B TFIFO3A TFIFO3B TFIFO2A TFIFO2B TFIFO1A TFIFO1B 019 R/W TPORT4 TPORT3 TPORT2 TPORT1 021 R/W 0 ECKMSK * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Bit 6 Bit 5 Bit 4 TranSwitch Test Register (set to 00H) SPOTPCLD ( TranSwitch Test Bits (set to 0000) ...
Page 101
... A3UAISI A2UAISI A1UAISI 0 A3UAISI A2UAISI A1UAISI 0 A3DH4E A2DH4E A1DH4E 0 A3DH4E A2DH4E A1DH4E 0 B3UAISI B2UAISI B1UAISI 0 B3UAISI B2UAISI B1UAISI 0 B3DH4E B2DH4E B1DH4E 0 B3DH4E B2DH4E B1DH4E Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 RnEN ANAnTx ANAnEN PRBSnEN FRDISn TXC-04252-MB Ed. 3, December 2000 Bit 0 0 ...
Page 102
... AnTCUQ AnTCAIS AnTCLM AnTCLL AnTCTM AnTCODI AnTCRDI 100 200 300 400 R 101 201 301 401 R 102 202 302 402 R 116 216 316 416 R * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 AnLOP AnSIZE AnNDF ...
Page 103
... Port n HDB3 Coding Errors (High Byte) - 103 of 148 - QE1M TXC-04252 Bit 2 Bit 1 Bit 0 BnRFI BnUNEQ BnSLER BnRFI BnUNEQ BnSLER BnNJ Counter Bn Rx Label Unused (00) Unused (00) BnTCODI BnTCRDI 0 BnTCODI BnTCRDI 0 Bit 2 Bit 1 Bit 0 TnLOS TnLOC TnDAIS TnLOS TnLOC TnDAIS TXC-04252-MB Ed. 3, December 2000 ...
Page 104
... B side TC (N2 (Z6)) 16-byte microprocessor-written trace message (XF0 - XFF) 540 5C0 640 6C0 R/W to 57F 5FF 67F 6FF Where for Port 1, 2 for Port 2, 3 for Port 3, 4 for Port 4. * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Bit 6 Bit 5 Bit 4 1BnRDI ...
Page 105
... Internal SPOT Processor Load Register: These bits are the upper 3 bits of the 11-bit register which is used as the offset address access for the SPOT Instruction RAM. During normal operation these bits must be written to 0. TranSwitch Test Register: These bits must be written 105 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 106
... NPIB 0 NPIC Note 1: The add bus will be forced to a high impedance state automatically when loss of clock is detected on the transmit clock signal selected by control bit DBPBT. TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Format Selection: The format selection is made according to the table given below ...
Page 107
... Transmit E1 Line Clock Inversion: A common control for the four ports enables transmit data to be clocked in on the negative (falling) clock edges enables transmit data to be clocked in on the positive (rising) clock edges. - 107 of 148 - QE1M TXC-04252 Action TXC-04252-MB Ed. 3, December 2000 ...
Page 108
... RAISE (cont.) 0 RCLKI TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Receive E1 Line AIS Enable: A common control for the four ports enables a receive E1 AIS to be sent from port n when internal defined alarms occur for a port AIS is an unframed all ones signal. For ...
Page 109
... A/B Drop Bus Parity Detected on Data Only: Common control bit for both buses causes parity to be calculated over the data byte only causes parity to be calculated over the data byte, SPE and C1J1V1 signals. Please refer to the table provided for DPE. - 109 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 110
... NULLZ 2 DDIND 1 UQAE 0 TOBWZ TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description A/B H1/ Byte AIS Enable: Common control for both the A and B Drop buses enables an AIS detected in either the SDH/SONET H1/H2 bytes the E1 bytes, to generate a receive E1 line AIS and transmit an RDI (when enabled). ...
Page 111
... This bit should only be set to 1 after a hardware reset (lead 155 or C5 software reset (control bit RESET above) has been activated. This bit is self-clearing and will reset to 0 after the Data RAM initialization is complete. See Note 1. - 111 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 112
... PORT4 2 PORT3 1 PORT2 0 PORT1 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Software Interrupt Indication indicates that a latched alarm has occurred for which the corresponding interrupt mask bit(s) is/are set to 1. External Clock Interrupt Indication: Enabled when written into the ECKMSK bit indicates that the external clock at input lead EXTCK has failed (i ...
Page 113
... Receive FIFO Error Status Interrupt Mask Bit enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred for a port n receive FIFO while PnMSK is set for port dis- ables a receive FIFO error alarm for port n from causing an interrupt. See Note 1. - 113 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 114
... Description Unused: This bit must be written to 0. External Clock Interrupt Mask Bit enables a hardware interrupt and software interrupt indications (INT and ETXCK) when an external clock failure alarm has occurred. See Note 1. A Side Interrupt Mask Bit enables the A Side Interrupt Indication (ASIDE) ...
Page 115
... AU-4 VC-4 signal. When control bit SE1AIS indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 025 hex, except the bits are latched. - 115 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 116
... A3DH4E 1 A2DH4E 0 A1DH4E 026 7-0 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Loss Of External Clock indicates an external loss of clock alarm when the external clock (present on lead 138) is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. Unused: These bits read out as 0. ...
Page 117
... AU-4 VC-4 signal. When control bit SE1AIS indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 029 hex, except the bits are latched. - 117 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 118
... Port 2 Leak 0A9 Port 3 Rate 0D9 Port 4 Value TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Internal Processor (SPOT) Loss of Clock: The 29.16 MHz clock inter- nally derived from the 58.32 MHz desynchronizer clock input (EXTCK) is monitored for loss of clock. Loss of clock is declared if this clock is stuck high or low for 1000 +/- 500 ns ...
Page 119
... QUIETn is low forces the data and clock output leads to a high impedance state. The four bits power and are reset must be written to these control bits to enable the port E1 outputs. Unused: This bit must be written 119 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 120
... Unused 3 V4EN 2-0 Unused TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description A Side Drop Bus Port n TU/VT Selection Output Enable enables the drop bus ADIND signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. ...
Page 121
... The number of consecutive events used for detection and recovery is determined by control bit V5AL10. A Drop Bus Port n Remote Failure Indication indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate. - 121 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 122
... Unused 0DE Port 4 3-2 Latched An Alarms 1-0 Unused TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description A Drop Bus Port n Unequipped Indication indicates that an Unequipped status has been detected in the V5 signal label (Bits 5 byte = 0) for the TU/VT selected in the A side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm ...
Page 123
... The two nibbles written into this register location will be from the same frame. Same alarms as the following address locations (7-1), except that these alarm states are latched. Unused: This bit reads out as indeterminate. - 123 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 124
... Port 2 REI 301 Port 3 Error 401 Port 4 Counter TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description A Drop Bus Port n Tandem Connection Unequipped Alarm unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more con- secutive frames ...
Page 125
... The number of consecutive events used for detection and recovery is determined by control bit V5AL10. B Drop Bus Port n Remote Failure Indication indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate. - 125 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 126
... Unused 0EE Port 4 3-2 Latched Bn Alarms 1-0 Unused TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description B Drop Bus Port n Unequipped Indication indicates that an Unequipped status has been detected in the V5 signal label (Bits 5 byte = 0) for the TU/VT selected in the B side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm ...
Page 127
... The two nibbles written into this register location will be from the same frame. Same alarms as the following address locations (7-1), except that these alarm states are latched. Unused: This bit reads out as indeterminate. - 127 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 128
... Port 2 REI 381 Port 3 Error 481 Port 4 Counter TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description B Drop Bus Port n Tandem Connection Unequipped Alarm unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more con- secutive frames ...
Page 129
... Transmit Port n AIS Detected indicates that line AIS (one or less zero in 256 bits) has been detected in the bit stream for port n. Recovery occurs when there are 3 or more zeros in 256 bits. Other than reporting the alarm, no action is taken. - 129 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 130
... Port 3 Counter 0D7 Port 4 High Order Byte TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Transmit Port n Coding Violation Counter: Low order byte of a 16-bit saturating counter which counts the number of coding errors that have occurred in the HDB3 line code. During a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated ...
Page 131
... Trace message comparison circuit enabled Transmit and receive J2 message segments are configured for a 64-byte message size. Micropro- cessor reads 64-byte segment. J2 comparison circuit and alarms are disabled. The Tandem Connection feature must be disabled by setting TCnEN=0. - 131 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 132
... TnRFI 1 TnRDIS 0 TnRDIP TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description Facility Loopback enables an E1 facility (side) loopback for port n. The E1 transmit clock and data output signals are looped back internally as the E1 receive clock and data input signals. The external E1 receive input signals are disabled ...
Page 133
... J2 Loss Of Lock Alarm (A1J2LOL, B1J2LOL) when J2AISEN Mismatch Alarm (A1J2TIM, B1J2TIM) when J2AISEN Unequipped Alarm (A1TCUQ, B1TCUQ Loss Of Lock Alarm (A1TCLL, B1TCLL Mismatch Alarm (A1TCTM, B1TCTM Loss Of Multiframe Alarm (A1TCLM, B1TCLM written to TC1RDI and written to TC1RDI. - 133 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 134
... TC ODI or TC RDI are sent only once for every 38 ms multiframe conceivable that these alarms may tog- gle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm. TXC-04252-MB Ed. 3, December 2000 DATA SHEET ...
Page 135
... Transmit V4 Byte Port n: The value written into this register will be trans- 591 Port 2 V4 mitted as the V4 byte. Bits 7-0 of the register correspond to bits 1-8 of the 611 Port 3 Byte V4 byte. 691 Port 4 DATA SHEET Description - 135 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 136
... Port 1 Message 2FF Port 2 Segments 3FF Port 3 4FF port 4 TXC-04252-MB Ed. 3, December 2000 DATA SHEET Description A Side Drop J2 and N2 (Z6) Message Segments: The following loca- tions store the received 64-byte J2 message when control bit J2nSIZE and the received 16-byte J2 message, and microprocessor-written ...
Page 137
... The 16-byte message is transmitted with no 640-64F (Port 3) specific starting address. 6C0-6CF (Port 4) 560-56F (Port 1) N2 (Z6) Message size configured for 16 bytes. 5E0-5EF (Port 2) The 16-byte message is transmitted with no 660-66F (Port 3) specific starting address. 6E0-6EF (Port 4) - 137 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 138
... INDEX LEAD #1 SEE DETAIL “A” 0 -10 DEGREES Figure 28. QE1M TXC-04252 160-Lead Plastic Quad Flat Package TXC-04252-MB Ed. 3, December 2000 DATA SHEET 81 TRANSWITCH TXC-04252AIPQ 40 25.35 (SQ) 28.00 (SQ) 31.20 (SQ) 0.15 DETAIL “A” Notes: 1. All linear dimensions are in millimeters. 0.88 2. All dimensions are nominal unless ...
Page 139
... Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° angle, or chamfered for A1 identification. 3. Size of array 16, JEDEC code MO-151-AAF-1 Figure 29. QE1M TXC-04252 208-Lead Plastic Ball Grid Array Package DATA SHEET Bottom View -E1- 16 ...
Page 140
... Proprietary TranSwitch Corporation Information for use Solely by its Customers. QE1M TXC-04252 ORDERING INFORMATION Part Number: TXC-04252AIPQ TXC-04252AIOG RELATED PRODUCTS TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). Provides complete STS-3/STM-1 frame synchronization on incoming 155 Mbit/s signals in a single low power CMOS unit ...
Page 141
... Web: www.atmforum.com Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel Fax Web: www.etsi.org - 141 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 142
... Piscataway, NJ 08854 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsu-cho Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo TXC-04252-MB Ed. 3, December 2000 DATA SHEET Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) Fax: (508) 650-1375 Web: www.mvip.org ...
Page 143
... Switched the position of the words con- nectivity and payload in the third line of the second paragraph. 62-67 Made changes in text. DATA SHEET Edition 3, December 2000 Edition 2, October 1997 Summary of the Change 5 ’ in first column of table and added Note 5. - 143 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 144
... Added the new row for Symbol 1BnRDI and changed ‘7-4’ to ‘7-5’ for Bit col- umn in first row of table. 133 Modified Description column for Symbol TCnEN. 138, 140 Removed second hyphen from device part number (now TXC-04252AIPQ). 139 Added Figure 29. 140 Added Part Number for PBGA under Ordering Information section. ...
Page 145
... TranSwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. DATA SHEET - NOTES - - 145 of 148 - QE1M TXC-04252 TXC-04252-MB Ed. 3, December 2000 ...
Page 146
... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - 146 - • • Fax: 203-926-9453 www.transwitch.com ...
Page 147
... Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453 e-mail (info@txc.com telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www ...
Page 148
... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...