TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 13

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

AAC1J1V1
Symbol
AA(7-0)
AASPE
AACLK
AAPAR
AAIND
AADD
160-Lead
Lead No.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
56, 58,
59, 60,
62, 63,
PQFP
64, 65
28
55
31
23
54
30
208-Lead
Lead No.
P10, T10
R9, N10,
P7, P8,
N8, N9,
PBGA
K2
R7
T7
L1
L4
J3
I/O/P Type *
O(T) CMOS
O(T) CMOS
O
O
I
I
I
CMOS
CMOS
4mA
4mA
4mA
4mA
TTL
TTL
TTL
DATA SHEET
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A Add Bus Clock: When the add bus timing mode is
selected, this input must be provided for add bus timing. This
clock operates at 19.44 MHz for STM-1/STS-3 operation,
and at 6.48 MHz for STS-1 operation. The add bus SPE indi-
cation (AASPE), and the C1J1V1 indication (AAC1J1V1) are
clocked in on falling edges of this clock. Add bus byte-wide
data (AA7-AA0), add indicator (AADD), and parity bit
(AAPAR) are clocked out on rising edges of the clock during
the time slots that correspond to the selected TU/VT. When
drop bus timing is selected, this input is disabled.
A Add Bus Parity Bit: An odd parity output signal that is
calculated over the byte-wide add data. This tristate lead is
only active when there is data being added to the add bus.
When control bit APE is 1, even parity is calculated.
A Add Bus Data Byte: Byte-wide data that corresponds to
the selected TU/VT.
A Add Bus SPE Indicator: When the add bus timing mode
is selected, this signal must be provided for add bus timing.
This signal must be high during each byte of the
STM-1/STS-3/STS-1 payload, and low during Transport
Overhead byte times.
A Add Bus C1J1V1 Indications: When the add bus timing
mode is selected, this signal must be provided for add bus
timing. An active high timing signal that carries
STM-1/STS-3/STS-1 starting frame and SPE information.
This signal works in conjunction with the AASPE signal. The
C1 pulse identifies the location of the first C1 byte in the
STM-1/STS-3 signal, and the C1 byte in the STS-1 signal,
when AASPE is low. The J1 signal identifies the starting
location of the J1 signal when AASPE is high. The J1 signal
identifies the location of the J1 byte. One or more V1 pulses
may be present depending upon the format. The V1 pulses
are used in place of the H4 byte as the multiframe indication.
A Add Bus TU/VT Selection Indication: Enabled when
control bit AAnEN is written with a 1. An active low signal
that is clocked out for the time slots determined by TU/VT
selection (TTUNn register) for each port (n=port number,
1-4).
A Add Bus Add Data Present Indicator: This normally
active low signal is present when output data to the A Add
bus is valid. It identifies the location of all of the TU/VT time
slots being selected. When control bit ADDI is 1, the indica-
tor is active high instead of active low.
Name/Function
Ed. 3, December 2000
TXC-04252
TXC-04252-MB
QE1M