TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 111

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

COMMON REGISTERS - PROVISIONING DESCRIPTIONS
Note 1: The control bits RESET, RESTSP and INITSP in address 015H should not be applied simultaneously, but only
Note 2: Control bits RESTAB and RESTBB may be applied at the same time (60H).
Address
014
015
serially (e.g., 80H followed by 01H, rather than 81H).
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
7-5
3-1
Bit
4
3
2
1
0
7
6
5
4
0
RESTBB
RESTSP
RESTAB
Symbol
UEAME
V5AL10
Unused
SE1AIS
PTALTE
Unused
HDWIE
RESET
INITSP
Unused: These bits must be written to 0.
Unequipped All Modes Enable: A 0 enables an unequipped channel or
an unequipped supervisory channel to be generated in the Multiplexer
Mode only, according to the table given below:
Drop
A 1 enables an unequipped channel or unequipped supervisory channel
to be transmitted only on the active bus for the TU/VT selected.
See control bits UCHnE and USCHnE below (Addresses 04A, 07A, 0AA,
0DA) for associated control functions.
Select E1AIS: A 1 disables the TOH H1/H2n AIS detection circuit and
enables the AIS detection circuit for the TOH E1n bytes. A 0 enables the
AIS detection circuit for the H1/H2n bytes. Here the value of n is 1 for an
STM-1 format and 1, 2 or 3 for an AU-3/STS-1 signal.
V5 Alarm Detection Select 10: A 1 selects 10 consecutive RDI asser-
tions for detection and recovery. A 0 selects 5 consecutive RDI asser-
tions for detection and recovery.
Pointer Tracking AIS to LOP Transition Enabled: A 1 enables the AIS
to LOP transition in the pointer tracking state machine, as required by
ETSI standards. A 0 will disable the transition, as required by Bellcore
and ANSI standards.
Hardware Interrupt Enable: A 1 enables the interrupt lead to be acti-
vated when an interrupt occurs.
Reset: A 1 clears to zero all controls, alarms, internal counters and per-
formance counters, sets control bits AAHZE and BAHZE to 1, and re-ini-
tializes the receive and transmit FIFOs. This bit is self-clearing, and will
reset to 0 after the reset cycle is completed. See Note 1.
Reset A Side Bus Alarms: A 1 clears the alarms associated with the A
side bus and the LEXTC alarm. This bit is self-clearing, and will reset to
0 after the reset cycle is completed. See Note 2.
Reset B Side Bus Alarms: A 1 clears the alarms associated with the B
side bus and SPOT alarms. This bit is self-clearing, and will reset to 0
after the reset cycle is completed. See Note 2.
Reset Internal Processor (SPOT): A 1 resets the SPOT processor,
without affecting its RAM. This bit will reset itself to 0 after the reset cycle
is completed. See Note 1.
Unused: These bits must be written to 0.
Initialize Internal Processor (SPOT) Data RAM: A 1 initializes the Data
RAM associated with the SPOT processor and resets the general pur-
pose registers of this processor. This bit should only be set to 1 after a
hardware reset (lead 155 or C5) or a software reset (control bit RESET
above) has been activated. This bit is self-clearing and will reset to 0
after the Data RAM initialization is complete. See Note 1.
A
B
Add
B
A
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DATA SHEET
be transmitted for the TU/VT selected on the A Bus.
be transmitted for the TU/VT selected on the B Bus.
Unequipped or unequipped supervisory channel can
Unequipped or unequipped supervisory channel can
Action
Description
Ed. 3, December 2000
TXC-04252
TXC-04252-MB
QE1M