TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 39

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. All output times are measured with a maximum 75 pF load capacitance.
2. One SPcyc equals two EXTCK clock cycles.
3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, result-
4. During a SPOT instruction read or data RAM read cycle, DTACK stays high after t
(The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.)
ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is
detected, QE1M tries to slow down the external microprocessor access rate by lengthening the DTACK pulse width
to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency
for the QE1M SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet).
DTACK settles to low after t
a. Use 16 wait states for a read or write access if the DTACK signal is not being used. Forcing a longer wait state
for every access may create unwanted delays in the internal process for the QE1M. Using the 16 wait states will
provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other
frequencies, use an equivalent number of wait states that equals approximately 640 ns.
b. Maintain no more than 16 microprocessor accesses per 125 s frame period.
c. Maintain a minimum of 600 ns between microprocessor accesses.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
D(3
)
. DTACK may go directly from a low to a high impedance state.
DATA SHEET
- 39 of 148 -
D(3)
. During a register read cycle,
Ed. 3, December 2000
TXC-04252
TXC-04252-MB
QE1M