TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 113

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

COMMON REGISTERS - INTERRUPT MASK DESCRIPTIONS
Note 1: Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register
Address
016
017
018
019
locations to which these interrupt masks apply. RPTnA or RPTnB is not required to be set to 1 to enable
an interrupt for AnRFI or BnRFI alarms. Control bit HDWIE must be set to 1 if a hardware interrupt is required.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
7, 5,
6, 4,
7, 5,
6, 4,
7, 6,
3, 2,
3, 1
2, 0
3, 1
2, 0
5, 4
1, 0
7-1
Bit
0
SPTMSK
TFIFOnA
TFIFOnB
TPORTn
Symbol
RFIFOn
Unused
RPTnA
(n=4-1)
RPTnB
(n=4-1)
(n=4-1)
(n=4-1)
(n=4-1)
(n=4-1)
Unused: These bits must be written to 0.
SPOT Status Interrupt Mask: A 1 enables a hardware interrupt (lead
INT/IRQ) and a software interrupt indication (INT) when a SPOT alarm
has occurred in any of the SPOT alarm register bits (address 028H, bits
7, 6 and 4). A 0 disables the SPOT alarms from causing an interrupt.
See Note 1.
Receive A Side Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has
occurred in an A-side port n alarm register while PnMSK is set for port n.
A 0 disables the A side receive alarms for port n from causing an inter-
rupt. See Note 1.
Receive B Side Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has
occurred in a B-side port n alarm register while PnMSK is set for port n.
A 0 disables the B side receive alarms for port n from causing an inter-
rupt. See Note 1.
Transmit FIFO Error A Side Status Interrupt Mask Bit: A 1 enables a
hardware interrupt and software interrupt indication (INT) when an alarm
has occurred for an A-side port n transmit FIFO while PnMSK is set for
port n. A 0 disables a transmit FIFO error A side alarm for port n from
causing an interrupt. See Note 1.
Transmit FIFO Error B Side Status Interrupt Mask Bit: A 1 enables a
hardware interrupt and software interrupt indication (INT) when an alarm
has occurred for a B-side port n transmit FIFO while PnMSK is set for
port n. A 0 disables a transmit FIFO error B side alarm for port n from
causing an interrupt. See Note 1.
Transmit Status Interrupt Mask Bit: A 1 enables a hardware interrupt
and software interrupt indication (INT) when an alarm has occurred for
one of the port n transmit alarms while PnMSK is set for port n. A 0 dis-
ables a transmit alarm from causing an interrupt. See Note 1.
Receive FIFO Error Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has
occurred for a port n receive FIFO while PnMSK is set for port n. A 0 dis-
ables a receive FIFO error alarm for port n from causing an interrupt.
See Note 1.
- 113 of 148 -
DATA SHEET
Description
Ed. 3, December 2000
TXC-04252
TXC-04252-MB
QE1M