TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 72

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
PRBS PATTERN GENERATOR AND ANALYZER
Each port has a data generator and analyzer for 2
tor is enabled when a 1 is written to control bit PRBSnEN. The PRBS pattern will be synchronous to the clock
driving the HDB3 decoder. When a 1 is written to ANAnEN control bit, the PRBS analyzer is enabled. When
control bit ANAnTx is 0, the analyzer will sample the receive NRZ clock and data (REC NRZ) signals. When
the control bit ANAnTx is 1, the internal transmit NRZ clock and data signals (XMIT NRZ) will be sampled by
the analyzer.
RESETS
The Quad E1 Mapper has several reset options. These include a full hardware and software device reset, par-
tial software resets, and counter software resets. All of the software reset bits are self-clearing (i.e., they do not
require 0 to be written to a register location after the reset is applied by setting the bit to 1). Note that the
self-clearing function requires the presence of the clock signal provided to the EXTCK lead (lead 138 or D10).
Upon power-up, when the RESET bit (address 015H, bit 7) is written with a 1, or an active low signal is placed
on the RESET lead (lead 155 or C5), the add bus data and the port E1 interfaces are forced to a high imped-
ance state until the device is initialized. The control bits AAHZE and BAHZE (address 010H, bits 5 and 4) must
be written with zeros to enable the add bus interfaces. The RnEN control bits must be programmed to 1 to acti-
vate the line interfaces. In addition, the AAIND, BAIND, AADD and BADD leads are forced off. All performance
counters are reset, and the alarms (except AnLOP and BnLOP) are reset. The control bits (except those
shaded in the Memory Map) are also forced to zero, and the various FIFOs are re-initialized. The shaded bits
are contained in the Data RAM, and these can be initialized by writing a 1 to INITSP (see Memory Map
Descriptions, address 015H, bit 0). A hardware reset can only be applied after the clocks are stable, and must
be present for a minimum duration of 150 ns.
Writing a 1 to the RnSETS software reset control bit for any of the ports resets the port n performance
counters, re-initializes the FIFO, and clears the alarms, except the AnLOP and BnLOP alarms, which will set
for port n. The loss of pointer alarms will recover when a valid pointer is received. The control bits will not be
reset.
Writing a 1 to the RnSETC counter reset control bit for any of the ports reset the performance counters for that
port. This feature allows the performance measurements to start at the same time for a port.
Writing a 1 to control bit RESTAB (address 015H, bit 6) resets the alarms for the A bus and for LEXTC (i.e.,
addresses 022H to 025H). Writing a 1 to control bit RESTBB (address 015H, bit 5) resets the alarms for the B
bus and the SPOT alarms (i.e., addresses 026H to 028H).
Note that a hardware reset will automatically trigger all the software reset bits. Software reset bit RESET will
trigger all RnSETS, all RnSETC, RESTAB and RESTBB automatically. A RnSETS will also automatically trig-
ger a RnSETC.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
DATA SHEET
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15
-1 PRBS patterns, as illustrated in 20. The PRBS genera-