TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 5

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers.
QE1M
DATA SHEET
TXC-04252
BLOCK DIAGRAM DESCRIPTION
The block diagram for the Quad E1 Mapper is shown in 1. The Quad E1 Mapper interfaces to four buses, des-
ignated as A Drop, B Drop, A Add, and B Add. The four buses run at the STM-1/STS-3 rate of 19.44 Mbyte/s,
or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous E1 signals are car-
ried in floating Virtual Tributary 2 (VT2) format in a Synchronous Transport Signal - 1 (STS-1), or in an STS-1
that is carried in a Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the E1 signals are car-
ried in floating mode Tributary Unit - 12 (TU-12) format in the STM-1 Virtual Container - 4 structure (VC-4)
using Tributary Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary
Unit Group -2 (TUG-2) mapping schemes. Four E1 signals can be dropped from one bus (A Drop or B Drop),
or from both of the drop buses, to the E1 lines. Four asynchronous E1 signals are converted into TU-12 or VT2
format and are added to either of the add buses, or both, depending upon the mode of operation. When the
Quad E1 Mapper is configured for dro
bus timing, the add buses are, by definition, byte- and multiframe-syn-
P
chronous with their like-named drop buses, but are delayed by one byte time because of internal processing.
For example, if a byte in the STM-1 Virtual Container - 4 structure (VC-4) using Tributary Unit Group - 3
(TUG-3), TU-12/VT2 is to be added to the A Add bus, the time of its placement on the bus is derived from the
A Drop bus timing, and from software instructions specifying which TU/VT number is being dropped/added.
When the device is configured for add bus timing, the add bus, parity, and add indicator signals are derived
from the add clock, C1J1V1 and SPE signals.
The A Receive block is identical to the B Receive block. The TU/VT Terminate block is repeated 8 times, two
for each port (A and B sides). The Destuff, Desync, and HDB3 Coder blocks are repeated four times, one for
each port. The interface between a drop bus and Receive block consists of 12 input leads, and an optional out-
put lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication making the sig-
nal a C1J1V1 indicator, an SPE indicator, and an odd parity bit for the last-named three signals. Parity is
selectable by control bits for even parity and for the data byte only. The output lead is an optional TU/VT select
indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine the
location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is low. A
single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is high.
Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in each
of the STS-1 signals.
The Quad E1 Mapper can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector
for determining the location of the V1 pulse. The V1 pulse location is used to determine the location of the
pointer byte V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur three
drop bus clock cycles every four frames following the J1 pulse when the SPE signal is high. For STS-3 opera-
tion, three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three
clock cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the
J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the
next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second
clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of
TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte location is
six clock cycles after the V1 pulse.
For STS-1 operation, one V1 pulse must be present if the C1J1V1 signal is used. The V1 pulse must occur on
the next clock cycle after the J1 pulse, and when the SPE signal is high. The J1 pulse identifies the J1 byte
location (defined as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle)
the TUs start. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the
V1 bytes for the 21 TU-12/VT2s are also aligned with respect to the V1 pulse (please see the first diagram in
the Operation - Multiplex Format and Mapping Information section).
Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream
SDH/SONET AIS indication. The Quad E1 Mapper can monitor either the TOH E1 bytes or the H1/H2 bytes for
an AIS indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected.
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TXC-04252-MB
Ed. 3, December 2000