TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 107

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Address
011
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
Bit
7
6
5
4
3
2
Symbol
SBTEN
DRPBT
LATEN
TCLKI
TAISE
ABD
Software Bus Timing Enable: This bit works in conjunction with control
bit DRPBT in bit 6 and the ABUST lead according to the following table
(where X = Don’t Care):
SBTEN
This SBTEN bit is reset to 0 upon power-up and by a device reset.
Drop Bus Timing: Enabled when a 1 is written to control bit SBTEN. A 1
selects the drop bus timing mode, while a 0 selects the add bus timing
mode. See table above.
Add Bus Delay: A 0 delays the add bus data with respect to the drop
bus by one clock cycle, when the drop bus or add bus timing modes are
selected. A 1 delays the add bus data with respect to the drop bus or add
bus by one additional clock cycle, for a total of two clock cycles.
Latch On Transitions Enable Bit: A 0 disables the states of the IPOS
and INEG control bits, and causes the event alarm bits (latched alarm
bits in the registers) to latch on the positive (1) level of an alarm. A 1
enables the states of the IPOS and INEG control bits in register 012H.
Transmit E1 Line AIS Enable: A common control for all four ports. A 1
enables an E1 AIS (unframed all ones) to be generated and sent from
port n to the SDH/SONET side when an E1 line input loss of signal, or
loss of clock, occurs for port n.
Transmit E1 Line Clock Inversion: A common control for the four ports.
A 0 enables transmit data to be clocked in on the negative (falling) clock
edges. A 1 enables transmit data to be clocked in on the positive (rising)
clock edges.
0
0
1
1
DRPBT
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DATA SHEET
X
X
0
1
ABUST
Low
High
X
X
Description
Add bus timing selected. Add bus data
derived from add bus timing signals.
Software control of bus timing disabled.
Drop bus timing selected. Add bus data
derived from like-named drop bus.
Software control of bus timing disabled.
Add bus timing selected. Add bus data
derived from add bus timing signals.
Hardware control of bus timing dis-
abled.
Drop bus timing selected. Add bus data
derived from like-named drop bus.
Hardware control of bus timing dis-
abled.
Action
Ed. 3, December 2000
TXC-04252
TXC-04252-MB
QE1M