TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 52

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
INTERRUPT STRUCTURE
The interrupt indication register (address 020H) contains the global software interrupt bit INT and other inter-
rupt indication bits. Each interrupt indication bit has an associated set of latched alarm bits. A mask bit is pro-
vided to enable the set of latched alarms to trigger their interrupt indication bit. For port alarms, the latched
alarms of each port are further divided into several groups. A second level of mask bit is provided for each of
these groups to mask out the interrupt indication bit of the port. For each interrupt indication bit, if its interrupt
mask bits are 1, and one or more of its associated latched alarm bits are set, the interrupt indication bit will
become 1; which in turn causes the software interrupt indication bit INT to become 1. The QE1M also gener-
ates a hardware interrupt at the tristate 8mA interrupt lead INT(INT/IRQ), lead 152 or D6, provided the hard-
ware interrupt enable bit (HWDIE) is 1.
Addresses 016H and 021H are the first set of interrupt mask registers. The additional mask registers for the
port alarms are contained in addresses 017H, 018H and 019H. Upon power-up, when the RESET bit (bit 7 in
address 015H) is written with a 1, or an active low is placed on the RESET lead (lead 155 or C5), all the inter-
rupt mask bits are cleared to 0. They must be initialized to 1 in order to enable the interrupt indication bits. Con-
trol bits IPOS, INEG and LATEN should also be programmed to determine how the latched alarms are to be
set.
Consider alarm AnAIS. Assume that HWDIE is 1, the interrupt masks for AnAIS are 1, the control bits IPOS
and LATEN are 1, and control bit INEG is 0. Since AnAIS is a port alarm, interrupt mask bit PnMSK and the
second level mask bit RPTnA should be set to 1. A positive transition on AnAIS causes the latched bit of AnAIS
to be set, which in turn sets the interrupt indication bit PORTn. Then, both software and hardware interrupts
occur.
When an interrupt occurs, the external microprocessor can determine the alarm that caused the interrupt by
reading the latched alarm registers that correspond to the interrupt indication bit and interrupt mask bit. The
read cycles allow the microprocessor to determine what alarm has been set. When the register containing the
latched alarm (e.g., AnAIS) has been read, the latched alarm bit is cleared, releasing the software interrupt
(INT and PORTn returning to 0) and hardware interrupt. If there is more than one alarm in more than one alarm
register, each of the corresponding latched alarm registers must be read before the interrupt is released. In
addition, the hardware and software interrupt may be released by writing a 0 to the mask bits that correspond
to the interrupt indication register. For AnAIS, the interrupt can be masked by writing 0 to PnMSK or to the
RPTnA bits.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
DATA SHEET
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