27C010 Fairchild, 27C010 Datasheet - Page 7

• Manufacturer Part Number: 27C010
• Description: 1 /048 /576-Bit (128K x 8) High Performance CMOS EPROM
• Manufacturer: Fairchild

Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are V
supply must be at 12.75V during the three programming modes,
and must be at 5V in the other three modes. The V
must be at 6.5V during the three programming modes, and at 5V
in the other three modes.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to
gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address access time
(t
at the outputs t
has been low and addresses have been stable for at least t
t
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 165 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRI-
STATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple memory connections. The 2-line control
function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on the V
EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be pro-
grammed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
OE
ACC
occur.
.
) is equal to the delay from CE to output (t
OE
after the falling edge of OE , assuming that CE
CC
PP
or A9 pin will damage the
and V
CE
PP
). Data is available
. The V
CC
power supply
PP
power
ACC
–
7
The EPROM is in the programming mode when the V
supply is at 12.75V and OE is at V
0.1 F capacitor be placed across V
spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 s
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 s pulse.
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be con-
nected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
V
CE input inhibits the other EPROM’s from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with V
programming and program verify.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of photo
currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s indentification code to aid in
programming. When the device is inserted in an EPROM pro-
grammer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The Manufacturer’s Identification code, shown in Table 2, specifi-
cally identifies the manufacturer and device type. The code for the
NM27C010 is “8F86”, where “8F” designates that it is made by
Fairchild Semiconductor, and “86” designates a 1 Megabit (128K
x 8) part.
The code is accessed by applying 12V 0.5V to address pin A9.
Addresses A1–A8, A10–A16, and all control pins are held at V
Address pin A0 is held at V
at V
O0–07. Proper code access is only guaranteed at 25 C
IL
and V
IH
for the device code. The code is read on the eight data pins,
PP
at 12.75V will program that EPROM. A TTL high level
PP
at 12.75V. V
IL
for the manufacturer’s code, and held
PP
IH
must be at V
PP
. It is required that at least a
, V
CC
to ground to suppress
CC
www.fairchildsemi.com
, except during
PP
power
5 C.
IL
.