HYS64V4120GU Siemens, HYS64V4120GU Datasheet - Page 6
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HYS64V4120GU
Manufacturer Part Number
HYS64V4120GU
Description
3.3V 4M x 64-Bit 2 BANK SDRAM Module 3.3V 4M x 72-Bit 2 BANK SDRAM Module
Manufacturer
Siemens
Datasheet
1.HYS64V4120GU.pdf
(11 pages)
Standby and Refresh Currents (T
Semiconductor Group
Operating Current
Burst Operating
power
Down Mode
power Down Mode
Current
Current
Parameter
Precharged Standby
Current in Power
Down Mode
Precharged Standby
Current in Non-
Down Mode
Active Standby
Current in Power
Active Standby
Current in Non-
Auto (CBR) Refresh
Self Refresh Current
Symbol
Icc2NS
Icc3NS
Icc2PS
Icc3PS
Icc2P
Icc2N
Icc3P
Icc3N
Icc1
Icc4
Icc5
Icc6
a
Burst length = 4, CL=3
trc>=trc(min.),
tck>=tck(min.), Io=0 mA
2 bank interleave operation
CKE<=VIL(max), tck>=tck(min.)
CKE<=VIL(max), tck=infinite
CKE>=VIH(min), tck>=tck (min.),
input changed once in 3 cycles
CKE>=VIH(min), tck=infinite,
no input change
CKE<=VIL(max), tck>=tck(min.)
CKE<=VIL(max), tck=infinite
CKE>=VIH(min), tck>=tck (min.)
input changed one time
CKE=>VIH(min),tck=infinite,
no input change
Burst length = full page,
trc = infinite, CL = 3,
tck>=tck (min.), Io = 0 mA
2 banks activated
trc>=trc(min)
CKE=<0,2V
= 0 to 70
Test Condition
o
C, VCC = 3.3V
6
4M x 64/72 SDRAM-Module
0.3V)
HYS64(72)V4120GU-10
X64
800
160
200
120
760
720
24
16
80
24
16
16
1)
X72
900
180
225
135
855
810
27
18
90
27
18
18
mA
mA
mA
mA CS=
mA
mA
mA
mA CS=
mA
mA
mA
mA
Note
High
High
1,2
1,2
1,2
1,2