CDP1881C Intersil Corporation, CDP1881C Datasheet - Page 5

• Manufacturer Part Number: CDP1881C
• Description: CMOS 6-Bit Latch and Decoder Memory Interfaces
• Manufacturer: Intersil Corporation

Dynamic Electrical Specifications
NOTES:
PROPAGATION DELAY TIMES
Chip Enable to Chip Select
MRD or MRW to Chip Select (Note 3)
CLOCK to Chip Select
CLOCK to Address
Memory Address to Chip Select
Memory Address to Address
1. Typical values are for T
2. Maximum limits of minimum characteristics are the values above which all devices function.
3. For CDP1881C type only.
CS0, CS1, CS2, CS3
CS0, CS1, CS2, CS3
CS0, CS1, CS2, CS3
PARAMETER
MRD OR MWR
MA0 - MA5
A8 - A11
CLOCK
A
= 25
CE
o
C.
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
(B) MRD OR MWR TO CHIP SELECT PROPAGATION DELAY (CDP1881C ONLY)
(C) MEMORY ADDRESS SETUP AND HOLD TIME
t
t
t
t
CDP1881C, CDP1882, CDP1882C
CLCL
CECS
t
MACS
t
CLCS
t
MCS
MAA
CLA
at T
(See Figure 1) (Continued)
t
MACL
A
= -40
t
FIGURE 3. TIMING WAVEFORMS
CECS
V
(V)
10
10
10
10
10
10
t
DD
5
5
5
5
5
5
CLA
t
MCS
o
t
C to +85
CLCS
t
CLMA
MIN
-
-
-
-
-
-
-
-
-
-
-
-
o
4-5
C, V
VALID CHIP ENABLE
DD
(NOTE 1)
CDP1882
TYP
100
100
100
75
45
75
40
65
65
75
80
40
5%, t
R
, t
(NOTE 2)
F
MAX
150
100
150
100
175
125
175
125
175
125
125
= 20ns, V
60
t
MACS
IH
MIN
= 0.7 V
-
-
-
-
-
-
-
-
-
-
-
-
CDP1881C, CDP1882C
t
t
MCS
MAA
(NOTE 1)
DD
TYP
, V
100
100
100
75
75
80
-
-
-
-
-
-
IL
t
= 0.3 V
MACS
t
MAA
t
CECS
(NOTE 2)
MAX
150
150
175
175
175
125
DD
-
-
-
-
-
-
, C
L
= 100pF,
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns