K7R161884B-FC25 Samsung semiconductor, K7R161884B-FC25 Datasheet - Page 2

• Manufacturer Part Number: K7R161884B-FC25
• Description: 512Kx36 & 1Mx18 QDR II b4 SRAM
• Manufacturer: Samsung semiconductor

FUNCTIONAL BLOCK DIAGRAM
FEATURES
K7R163684B
K7R161884B
D(Data in)
ADDRESS
R
W
BW
K
K
C
C
512Kx36-bit, 1Mx18-bit QDR
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
• Separate independent read and write data ports
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
• Two input clocks for output data(C and C) to minimize
• Two echo clocks (CQ and CQ) to enhance output data
• Single address bus.
• Byte write (x18, x36) function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 13x15mm
Notes: 1. Numbers in ( ) are for x18 device
with concurrent read and write operation
freguency scaling.
1.8V+0.1V/-0.1V for 1.8V I/O.
rising edges only.
clock-skew and flight-time mismatches.
traceability.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
X
4 (or 2)
36 (or 18)
17 (or 18)
LOGIC
DATA
CTRL
REG
ADD
REG
GEN
CLK
(or 18)
17
SELECT OUTPUT CONTROL
TM
II b4 SRAM
72(or 36)
WRITE DRIVER
MEMORY
512Kx36
(1Mx18)
ARRAY
512Kx36 & 1Mx18 QDR
- 2 -
Organization
72(or 36)
X36
X18
(or 36)
(or 36)
72
72
K7R163684B-FC30
K7R163684B-FC25
K7R163684B-FC20
K7R163684B-FC16
K7R161884B-FC30
K7R161884B-FC25
K7R161884B-FC20
K7R161884B-FC16
Number
Part
(or 72)
144
TM
Cycle
Time
3.3
4.0
5.0
6.0
3.3
4.0
5.0
6.0
II b4 SRAM
(Echo Clock out)
Access
Time
36 (or 18)
0.45
0.45
0.45
0.50
0.45
0.45
0.45
0.50
Q(Data Out)
CQ, CQ
July. 2004
Rev 3.1
Unit
ns
ns
ns
ns
ns
ns
ns
ns