AS7C33128PFD32B-133TQCN ALSC [Alliance Semiconductor Corporation], AS7C33128PFD32B-133TQCN Datasheet - Page 6
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AS7C33128PFD32B-133TQCN
Manufacturer Part Number
AS7C33128PFD32B-133TQCN
Description
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
1.AS7C33128PFD32B-133TQCN.pdf
(19 pages)
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Write All Bytes
Write Byte a
Write Byte c and d
Read
Snooze mode
Read
Write
Deselected
1
2
3
4
1/31/05; v.1.1
st
nd
rd
th
Address
Address
Address
Address
Operation
Function
Interleaved burst address (LBO = 1)
A1 A0
0 0
0 1
1 0
1 1
ZZ
GWE
H
L
L
L
L
H
H
H
H
H
L
A1 A0
0 1
0 0
1 1
1 0
BWE
X
H
L
L
L
L
OE
A1 A0
X
H
X
X
L
1 0
1 1
0 0
0 1
BWE
BWa
Alliance Semiconductor
X
H
X
H
L
L
Din, High-Z
A1 A0
,
I/O Status
BWn
1 1
1 0
0 1
0 0
High-Z
High-Z
High-Z
Dout
BWb
= internal write signal.
X
L
H
H
X
H
1
2
3
4
st
nd
rd
th
Address
Address
Address
Address
BWc
X
H
X
H
L
L
®
Linear burst address (LBO = 0)
BWd
X
H
X
H
L
L
A1 A0
0 0
0 1
1 0
1 1
A1 A0
0 1
1 0
1 1
1 0
A1 A0
AS7C33128PFD32B
AS7C33128PFD36B
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
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