AS7C33128PFD32B-133TQCN ALSC [Alliance Semiconductor Corporation], AS7C33128PFD32B-133TQCN Datasheet - Page 7
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AS7C33128PFD32B-133TQCN
Manufacturer Part Number
AS7C33128PFD32B-133TQCN
Description
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
1.AS7C33128PFD32B-133TQCN.pdf
(19 pages)
Synchronous truth table
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3
4 ZZ pin is always Low.
For write operation following a READ,
CE0
1/31/05; v.1.1
H
X
X
X
X
H
H
H
H
X
H
X
H
L
L
L
L
L
L
L
L
L
1
CE1
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
L
L
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
[4]
X
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
L
OE
ADSC
must be high before the input data set up time and held high throughout the input hold time
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
ADV
Alliance Semiconductor
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
WRITE
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
[2]
OE
X
X
X
X
X
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
®
Address accessed
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Next
Next
Next
Next
Next
Next
NA
NA
NA
NA
NA
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
CLK
AS7C33128PFD32B
AS7C33128PFD36B
Continue write
Continue write
Continue read
Continue read
Continue read
Continue read
Suspend write
Suspend write
Suspend read
Suspend read
Suspend read
Suspend read
Begin write
Begin read
Begin read
Begin read
Begin read
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
P. 7 of 19
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DQ
D
Q
Q
Q
Q
Q
Q
D
D
D
D
3