EVAL-AD1833EB AD [Analog Devices], EVAL-AD1833EB Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD1833EB
• Description: Multichannel 24-Bit, 192 kHz, DAC
• Manufacturer: AD [Analog Devices]

0000
DAC CONTROL REGISTER I
De-Emphasis
The AD1833 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam-
pling rates. The filters may be selected by writing to Control
Bits 9 and 8 in DAC Control Register I, see Table III.
Data Serial Interface Mode
The AD1833’s serial data interface is designed to accept data in
a wide range of popular formats including I
(RJ), left justified (LJ) and flexible DSP modes. The L/RCLK
pin acts as the word clock (or Frame Sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1-3 pins. The serial mode
settings may be selected by writing to Control Bits 7 through 5
in DAC Control Register I, see Table IV.
Bit 7
0
0
0
0
1
1
1
1
Address
15–12
Must be programmed to zero.
Table IV. Data Serial Interface Mode Settings
Bit 9
0
0
1
1
11
0
Reserved
Bit 6
0
0
1
1
0
0
1
1
Table III. De-Emphasis Settings
10
0
Bit 8
0
1
0
1
Bit 5
0
1
0
1
0
1
0
1
De-Emphasis
9–8
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
De-Emphasis
Disabled
44.1 kHz
32 kHz
48 kHz
Serial Mode
I
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
AUX Mode
Reserved
2
2
S
S, right justified
Serial Mode
7–5
000 = I
001 = RJ
010 = DSP
011 = LJ
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = AUX Mode
111 = Reserved
Table II. DAC Control I
2
S
DAC Word Width
The AD1833 will accept input data in three separate word-
lengths—16, 20, and 24 bits. The word-length may be selected
by writing to Control Bits 4 and 3 in DAC Control Register I,
see Table V.
Power-Down Control
The AD1833 can be powered down by writing to Control Bit 2
in DAC Control Register I, see Table VI. The power-down/
reset bit is not latched when the CLATCH is brought high to
latch the entire word, but only after the following low-to-high
CLATCH transition. Therefore, to put the part in power-down,
or to bring it back up from power-down, the command should
be written twice.
Interpolator Mode
The AD1833’s DAC interpolators can be operated in one of
three modes—8×, 4×, or 2× corresponding with 48 kHz, 96 kHz,
and 192 kHz modes respectively. The Interpolator Mode may
be selected by writing to Control Bits 1 and 0 in DAC Control
Register I, see Table VII.
Bit 1
0
0
1
1
Bit 4
0
0
1
1
Data Word
Width
4–3
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Bit 2
0
1
Table VII. Interpolator Mode Settings
Function
Table VI. Power-Down Control
Table V. Word Length Settings
Bit 0
0
1
0
1
Bit 3
0
1
0
1
Power-Down
RESET
2
0 = Normal
1 = PWRDWN
Power-Down Setting
Normal Operation
Power-Down Mode
Interpolator Mode
8× (48 kHz)
2× (192 kHz)
4× (96 kHz)
Reserved
Word Length
24 Bits
20 Bits
16 Bits
Reserved
Interpolator
Mode
1–0
00 = 8× (48 kHz)
01 = 2× (192 kHz)
10 = 4× (96 kHz)
11 = Reserved
AD1833