EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet
EVAL-AD1928EB
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EVAL-AD1928EB Summary of contents
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FEATURES PLL-generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N 3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to ...
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AD1928 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 5 Digital Input/Output Specifications........................................... 5 ...
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SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) 3 Temperature range As specified in Master clock 12.288 MHz (48 kHz f Input ...
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AD1928 Parameter Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Specifications measured at a case temperature of 130°C. Table ...
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CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Transconductance DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < +130°C, DVDD = 3.3 V ± 10%. A Table 4. Parameter High Level Input Voltage ( Low Level Input Voltage ( Input ...
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AD1928 DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay TIMING SPECIFICATIONS −40°C < ...
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Parameter SPI PORT t CCH t CCL f CCLK t CDS t CDH t CLS t CLH t CLHIGH t COE t COD t COH t COTS DAC SERIAL PORT t DBH t DBL t DLS t DLH t DLSKEW ...
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AD1928 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under the Absolute ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND MCLKI/XI MCLKO/XO AGND AVDD OL3 OR3 OL4 OR4 PD/RST DSDATA4 DGND CONNECT Table 10. Pin Function Descriptions Pin No. Input/Output Mnemonic 1 I AGND 2 I MCLKI/ MCLKO/XO 4 ...
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AD1928 Pin No. Input/Output Mnemonic 28 O OL1 29 O OR1 30 O OL2 31 O OR2 32 I AGND 33 I AVDD 34 I AGND 35 O FILTR 36 I AGND 37 I AVDD ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 2000 4000 6000 8000 10000 12000 FREQUENCY (Hz) Figure 3. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD1928 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 192 kHz Rev Page –2 –4 –6 –8 ...
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THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are two analog-to-digital converter (ADC) channels in the AD1928, configured as a stereo pair with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 ...
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AD1928 ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN The function of the RST pin sets ...
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POWER SUPPLY AND VOLTAGE REFERENCE The AD1928 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the ...
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AD1928 Table 12. Pin Function Changes in TDM-AUX Mode Mnemonic Stereo Modes ADCTDMOUT NC ASDATA1 ADC1 Data Output DSDATA1 DAC1 Data Input DSDATA2 DAC2 Data Input DSDATA3 DAC3 Data Input DSDATA4 DAC4 Data Input ALRCLK ADC LRCLK Input/Output ABCLK ADC ...
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ALRCLK ABCLK DSDATA1 DAC L1 DAC R1 (TDM_IN) 2 ON-CHIP ADC CHANNELS ADCTDMOUT UNUSED UNUSED (TDM_OUT) 32 BITS MSB DLRCLK LEFT (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ALRCLK ABCLK 2 ON-CHIP ADC CHANNELS AUXILIARY ADC ...
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AD1928 ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM_IN) 2 ON-CHIP ADC CHANNELS ADCTDMOUT UNUSED UNUSED ADC L1 ADC R1 (TDM_OUT) DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ASDATA1 MSB (AUX1_OUT) DSDATA4 MSB (AUX2_OUT) ...
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DAISY-CHAIN MODE The AD1928 also allows a daisy-chain configuration to expand the system to 4 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512 f . The first eight slots of the DAC S ...
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AD1928 DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 DAC L1 DAC R1 (IN) DSDATA2 (OUT) DSDATA3 DAC L3 DAC R3 (IN) DSDATA4 (OUT) 32 BITS MSB FIRST SECOND DSP AD1928 AD1928 Figure 19. Dual-Line ...
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ALRCLK ABCLK 2 ADC CHANNELS OF SECOND IC IN THE CHAIN ADCTDMOUT (TDM_OUT OF THE SECOND AD1928 UNUSED UNUSED ADC L1 ADC R1 UNUSED UNUSED ADC L1 ADC R1 IN THE CHAIN) ASDATA1 (TDM_IN OF THE SECOND AD1928 UNUSED UNUSED ...
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AD1928 t DBH DBCLK t DBL t DLS DLRCLK t DLSKEW t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATAx 2 I S-JUSTIFIED MODE DSDATAx RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ALSKEW t ABDD ASDATA ...
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Table 13. Pin Function Changes in TDM-AUX Mode (Replication of Table 12) Mnemonic Stereo Modes ADCTDMOUT NC ASDATA1 ADC1 Data Output DSDATA1 DAC1 Data Input DSDATA2 DAC2 Data Input DSDATA3 DAC3 Data Input DSDATA4 DAC4 Data Input ALRCLK ADC LRCLK ...
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AD1928 CONTROL REGISTERS DEFINITIONS 2 C and SPI ports. The global address for the AD1928 is 0x04, shifted left one bit due to the R/ W bit. All The format is the same for I registers are reset to 0, ...
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Table 17. PLL and Clock Control 1 Register Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS ...
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AD1928 Table 20. DAC Control 2 Register Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4 Reserved ...
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ADC CONTROL REGISTERS Table 23. ADC Control 0 Register Bit Value Function 0 0 Normal operation 1 Power down 1 0 Off Reserved 3 0 Reserved 4 0 Unmute 1 Mute 5 0 Unmute 1 Mute ...
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AD1928 Table 25. ADC Control 2 Register Bit Value Function 0 0 50/50 (allows 32, 24, 20, 16 bit clocks (BCLKs) per channel 1 Pulse (32 BCLKs per channel Drive out on falling edge (DEF) 1 Drive out ...
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ADDITIONAL MODES The AD1928 offers several additional modes for board-level design enhancements. To reduce the EMI in board-level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM data transmission ...
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AD1928 APPLICATION CIRCUITS Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the 120pF 600Z 5.76kΩ 5.76kΩ AUDIO INPUT ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1, 2 AD1928YSTZ −40°C to +105° AD1928YSTZ-RL −40°C to +105°C EVAL-AD1928EB EVAL-AD1928EBZ RoHS Compliant Part. 2 Single-ended output; SPI control port. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW 0.20 (PINS DOWN) 0.09 7° ...
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AD1928 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...