EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD1928EB
• Description: 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
• Manufacturer: AD [Analog Devices]

AD1928
CONTROL REGISTERS
DEFINITIONS
The format is the same for I
registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register
parameter is the default setting.
Table 14. Register Format
Bit
Table 15. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
0
2:1
4:3
6:5
7
Global Address
23:17
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
ADC Control 0
ADC Control 1
ADC Control 2
Function
Normal operation
Power-down
Input 256 (×44.1 kHz or 48 kHz)
Input 384 (×44.1 kHz or 48 kHz)
Input 512 (×44.1 kHz or 48 kHz)
Input 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × f
512 × f
Off
MCLKI/XI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
2
C and SPI ports. The global address for the AD1928 is 0x04, shifted left one bit due to the R/ W bit. All
S
S
VCO output
VCO output
R/W
16
Rev. 0 | Page 24 of 32
Internal master clock enable
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Register Address
15:8
Data
7:0