EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD1928EB
• Description: 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
• Manufacturer: AD [Analog Devices]

AD1928
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
DAC INTERPOLATION FILTER
TIMING SPECIFICATIONS
−40°C < T
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND
RESET
PLL
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
t
f
t
t
Lock Time
256 f
MH
MCLK
PDR
PDRR
S
VCO Clock Output Duty Cycle
A
< +130°C, DVDD = 3.3 V ± 10%.
Mode
All modes, typ @ 48 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
Condition
MCLK duty cycle
MCLK frequency
RST low
RST recovery
MCLK and LR
clock input
MCLKO/XO pin
Rev. 0 | Page 6 of 32
Comments
DAC/ADC clock source = PLL clock @ 256 f
384 f
DAC/ADC clock source = direct MCLK @ 512 f
(bypass on-chip PLL)
PLL mode, 256 f
Direct 512 f
Reset to active output
S
, 512 f
S
S
, and 768 f
mode
S
Factor
0.4375 f
0.5 f
0.5625 f
22.9844/f
0.4535 f
0.3646 f
0.3646 f
0.5 f
0.5 f
0.5 f
0.5465 f
0.6354 f
0.6354 f
25/f
11/f
8/f
reference
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Min
79
35
70
70
70
S
,
Typ
21
±0.015
24
27
479
22
70
24
48
96
26
61
122
521
115
42
S
Min
40
40
6.9
15
4096
40
Max
±0.01
±0.05
±0.1
Max
60
60
13.8
27.6
10
60
Unit
kHz
dB
kHz
kHz
dB
μs
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
Unit
%
%
MHz
MHz
ns
t
ms
%
MCLK