EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD1928EB
• Description: 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
• Manufacturer: AD [Analog Devices]

Parameter
SPI PORT
DAC SERIAL PORT
ADC SERIAL PORT
AUXILIARY INTERFACE
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCLK
CCH
CCL
CDS
CDH
CLS
CLH
CLHIGH
COE
COD
COH
COTS
DBH
DBL
DLS
DLH
DLSKEW
DDS
DDH
ABH
ABL
ALS
ALH
ALSKEW
ABDD
AXDS
AXDH
DXDD
XBH
XBL
DLS
DLH
Condition
CCLK high
CCLK low
CCLK frequency
CIN setup
CIN hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tristate
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Rev. 0 | Page 7 of 32
To DBCLK rising, slave mode
To ABCLK rising, slave mode
Comments
See Figure 11, except where otherwise noted
f
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK falling
Not shown in Figure 11
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 11
From CCLK falling
See Figure 24
Slave mode
Slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
Slave mode
Slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 11
Min
35
35
10
10
10
10
10
30
10
10
10
5
−8
10
5
10
10
10
5
−8
10
5
10
10
10
5
Max
10
30
30
30
+8
+8
18
18
AD1928
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns