EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD1928EB
• Description: 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
• Manufacturer: AD [Analog Devices]

Table 17. PLL and Clock Control 1 Register
Bit
0
1
2
3
7:4
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit
0
2:1
5:3
7:6
Table 19. DAC Control 1 Register
Bit
0
2:1
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0000
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Function
Normal operation
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Function
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
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Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read only)
Description
Power-down
Sample rates
SDATA delay (BCLK periods)
Serial format
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
AD1928