EVAL-AD5533EB AD [Analog Devices], EVAL-AD5533EB Datasheet

no-image

EVAL-AD5533EB

Manufacturer Part Number
EVAL-AD5533EB
Description
32-Channel Precision Infinite Sample-and-Hold
Manufacturer
AD [Analog Devices]
Datasheet
a
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
FEATURES
Infinite Sample-and-Hold Capability to
Infinite Sample-and-Hold Total Unadjusted Error
High Integration:
Per Channel Acquisition Time of 16 s Max
Adjustable Voltage Output Range
Output Impedance 0.5
Output Voltage Span 10 V
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Parallel Interface
Temperature Range –40 C to +85 C
APPLICATIONS
Optical Networks
Automatic Test Equipment
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
32-Channel DAC in 12 mm
TRACK / RESET
DAC GND
SER / PAR
DGND
AGND
BUSY
12 mm CSPBGA
V
IN
AD5533B
SCLK
0.018% Accuracy
INTERFACE
CONTROL
FUNCTIONAL BLOCK DIAGRAM
DV
LOGIC
D
CC
IN
ADC
AV
D
OUT
CC
2.5 m V
REF IN REF OUT
SYNC/CS
DAC
DAC
DAC
GENERAL DESCRIPTION
The AD5533B combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage on
the common input pin, V
tation transferred to a chosen DAC register. V
is then updated to reflect the new contents of the DAC register.
Channel selection is accomplished via the parallel address inputs
A0–A4 or via the serial input port. The output voltage range is
determined by the offset voltage at the OFFS_IN pin and the gain
of the output amplifier. It is restricted to a range from V
to V
The device is operated with AV
to +5.25 V, V
+16.5 V and requires a stable 3 V reference on REF_IN as well
as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. Precision infinite droopless sample-and-hold capability.
2. The AD5533B is available in a 74-lead CSPBGA with a
3. In infinite sample-and-hold mode, a total unadjusted error of
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
ADDRESS INPUT REGISTER
body size of 12 mm
± 2.5 mV is achieved by laser-trimming on-chip resistors.
A4 –A0
DD
– 2 V because of the headroom of the output amplifier.
OFFS IN
CAL
Infinite Sample-and-Hold
SS
= –4.75 V to –16.5 V, and V
OFFSET SEL
V
DD
32-Channel Precision
V
SS
IN
12 mm.
, is sampled and its digital represen-
CC
OFFS OUT
WR
V
V
OUT
OUT
= +5 V ± 5%, DV
0
31
© Analog Devices, Inc., 2002
AD5533B
DD
OUT
= +8 V to
www.analog.com
CC
for this DAC
= +2.7 V
SS
*
+ 2 V

Related parts for EVAL-AD5533EB

EVAL-AD5533EB Summary of contents

Page 1

FEATURES Infinite Sample-and-Hold Capability to Infinite Sample-and-Hold Total Unadjusted Error High Integration: 32-Channel DAC CSPBGA Per Channel Acquisition Time Max Adjustable Voltage Output Range Output Impedance 0.5 Output Voltage Span 10 ...

Page 2

AD5533B –SPECIFICATIONS Output Range from – All outputs unloaded. All specifications Parameter ANALOG CHANNEL Nonlinearity IN OUT Total Unadjusted Error (TUE) Gain Offset Error ANALOG ...

Page 3

Parameter DIGITAL OUTPUTS (BUSY OUT Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS Power Supply Voltages ...

Page 4

AD5533B TIMING CHARACTERISTICS PARALLEL INTERFACE Limit MIN 1, 2 Parameter (B Version NOTES 1 See Parallel Interface Timing ...

Page 5

SERIAL INTERFACE TIMING DIAGRAMS t 1 SCLK SYNC MSB Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes SCLK SYNC t ...

Page 6

... AD5532ABC-5 32 DACs, 32-Channel ISHA * AD5532BBC-1 32 DACs, 32-Channel Precision ISHA * EVAL-AD5533EB AD5532/AD5533 Evaluation Board *Separate Data Sheet CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5533B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

Page 7

CSPBGA Ball Number Name A1 NC CS/SYNC A5 A6 DVCC A7 SCLK A8 OFFSET_SEL BUSY A9 TRACK/RESET A10 A11 NC* B1 VO16 B2 NC DGND B7 DIN ...

Page 8

AD5533B Pin Function AGND (1–2) Analog GND Pins AV (1–2) Analog Supply Pins. Voltage range from 4. 5. (1–4) V Supply Pins. Voltage range from 16 (1–4) V ...

Page 9

TERMINOLOGY Nonlinearity IN OUT This is a measure of the maximum deviation from a straight line passing through the endpoints of the V IN function expressed as a percentage of the full-scale span. Total Unadjusted ...

Page 10

AD5533B–Typical Performance Characteristics 0.0024 0.0020 REFIN 0.0016 OFFS_IN 0.0012 0.0008 0.0004 0.0000 –0.0004 –0.0008 –0.0012 –0.0016 –0.0020 –0.0024 0.1 V – TPC Accuracy ...

Page 11

FUNCTIONAL DESCRIPTION The AD5533B can be thought of as consisting of an ADC and 32 DACs in a single package. The input voltage V and converted into a digital word. The digital result is loaded into one of the DAC ...

Page 12

AD5533B Reset Function The reset function on the AD5533B can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low-going pulse of between 90 ns and 200 ns to the ...

Page 13

MSB MODE BIT 1 MSB 1 0 MODE BITS b. Input Serial Interface (Acquire and Readback Mode) MSB 1 1 MODE BITS DB13–DB0 Bit These are used in both readback modes to read a 14-bit word from the addressed DAC ...

Page 14

AD5533B readback, 16 bits of data are clocked out of the AD5533B on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK ignored. The valid 14 bits of data will be ...

Page 15

MEASUREMENT ISHA ACTIVE ISHA LOAD ISHA STORED DATA DRIVER AND INHIBIT ISHA PATTERN FORMATTER ISHA PERIOD GENERATION AND DELAY COMPARE TIMING REGISTER COMPARATOR SYSTEM BUS ISHAs Figure 13. AD5533B in an ATE System Typical Application Circuit The AD5533B can be ...

Page 16

AD5533B A1 1.70 MAX Revision History Location 9/02—Data Sheet changed from REV REV. A. Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . ...

Related keywords