LF2246 LODEV [LOGIC Devices Incorporated], LF2246 Datasheet - Page 2

• Manufacturer Part Number: LF2246
• Description: 11 x 10-bit Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
SIGNAL DEFINITIONS
Power
V
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
D1
D1–D4 are 10-bit data input registers.
The LSB is D
C1
C1–C4 are 11-bit coefficient input regis-
ters. The LSB is C
Outputs
S
The current 16-bit result is available on
the S
15–0
F
F
CC
10–0
9–0
IGURE
IGURE
and GND
15–0
— Data Output
–D4
(Sign)
(Sign)
–C4
–2
–2
9
9
(Sign)
(Sign)
–2
–2
outputs (Figure 1b).
0
15 14 13
9
15 14 13
9–0
1
1
10–0
A
2
B
15
6
2
8
8
–1
. I
. O
— Data Input
N0
8
2
2
— Coefficient Input
14
5
2
2
(Figure 1a).
7
7
–2
NPUT
Data
7
2
N0
2
Fractional Two’s Complement (FSEL = 0)
Fractional Two’s Complement (FSEL = 0)
UTPUT
13
4
Integer Two’s Complement (FSEL = 1)
Integer Two’s Complement (FSEL = 1)
(Figure 1a).
12 11
12 11
2
2
12
3
F
2
2
2
2
ORMATS
–7
2
2
F
2
11
2
ORMATS
2
2
1
1
–8
1
10 9
2
10 9
2
10
1
2
2
0
0
–9
0
2
2
0
9
2
2
8
8
–1
8
Controls
ENB1–ENB4 — Input Enable
The ENB
either or both the D
be updated on each clock cycle. When
ENB
both strobed by the next rising edge of
CLK. When ENB
is LOW, register D
register C
ENSEL are HIGH, register D
and register C
ENSEL — Enable Select
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
OEN — Output Enable
When the OEN signal is LOW, the cur-
rent data in the output register is avail-
able on the S
HIGH, the outputs are in a high-imped-
ance state.
2
2
7
7
–2
7
2
(Sign)
2
N
(Sign)
6
6
–2
–2
–3
10 9
10 9
6
is LOW, registers D
10
1
2
2
5
N
5
–4
5
N
2
2
(
0
9
N
2
is held. If both ENB
2
4
4
–5
= 1, 2, 3, or 4) input allows
15–0
Coefficient
2
4
2
N
8
8
–1
8
2
is strobed (Table 1).
2
3
3
N
–6
3
2-12
pins. When OEN is
N
is HIGH and ENSEL
2
N
2
and C
2
2
–7
2
2
2
is strobed while
2
2
–7
2
2
2
1
1
–8
1
2
N
N
2
1
1
–8
1
2
and C
registers to
2
0
0
–9
0
N
2
2
0
0
–9
0
is held,
N
N
and
are
X = “Don’t Care”
‘
OCEN — Clock Enable
When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register’s
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.
FSEL — Format Select
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is per-
formed on the result. This allows sum-
mations without propagating roundoff
errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
previous products, without additional
rounding.
N
T
ENB1-4
’ = 1, 2, 3, or 4
ABLE
Video Imaging Products
1
1
0
11 x 10-bit Image Filter
1. I
ENSEL
NPUT
1
0
X
R
INPUT REGISTER
Data ‘
Coefficient ‘
None
EGISTER
08/16/2000–LDS.2246-K
N
HELD
’
LF2246
C
ONTROL
N
’