EVAL-AD9388AFEZ_1 AD [Analog Devices], EVAL-AD9388AFEZ_1 Datasheet - Page 15

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EVAL-AD9388AFEZ_1

Manufacturer Part Number
EVAL-AD9388AFEZ_1
Description
10-Bit Integrated, Multiformat, HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface
Manufacturer
AD [Analog Devices]
Datasheet
Pin No.
2
3
4
5
6
7
8
9
10
48
124
1
G = ground, P = power, I = input, and O = output.
Mnemonic
SPDIF
I2S0
I2S1
I2S2
I2S3
LRCLK
SCLK
MCLKOUT
EXT_CLAMP
EXT_CLK
RTERM
Type
O
O
O
O
O
O
O
O
I
I
I
1
Rev. B | Page 15 of 28
Description
SPDIF Digital Audio Output.
I
I
I
I
LRCLK, Data Output Clock for Left and Right Audio Channels.
Audio Serial Clock Output.
Audio Master Clock Output.
External Clamp Signal. This is an optional mode of operation for the AD9388A.
Clock Input for External Clock and Clamp Mode. This is an optional mode of
operation for the AD9388A.
Sets Internal Termination Resistance. Connect this pin to TGND using a 500 Ω
resistor.
2
2
2
2
S Audio (Channel 1 and Channel 2).
S Audio (Channel 3 and Channel 4).
S Audio (Channel 5 and Channel 6).
S Audio (Channel 7 and Channel 8).
AD9388A

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