EVAL-ADN2891EB AD [Analog Devices], EVAL-ADN2891EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADN2891EB
• Description: 3.3 V, 3.2 Gbps, Limiting Amplifier
• Manufacturer: AD [Analog Devices]

ADN2891
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane
with filled vias.
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Exposed
Pad
1
P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
AVCC
THRADJ
LOS
Mnemonic
PIN
NIN
AVEE
CAZ1
CAZ2
DRVEE
OUTN
OUTP
DRVCC
SQUELCH
RSSI_OUT
PD_VCC
PD_CATHODE
Pad
I/O Type
P
AI
AI
P
AO
AI
AI
DO
P
DO
DO
P
DI
AO
P
AO
P
1
Descriptions
Analog Power Supply.
Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
Analog Ground.
LOS Threshold Adjust Resistor.
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
LOS Detector Output, Open Collector.
Output Buffer Ground.
Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination.
Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination.
Output Buffer Power Supply.
Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor.
Average Current Output.
Power Input for RSSI Measurement.
Photodiode Bias Voltage.
Connect to Ground.
AVCC
AVEE
PIN
NIN
Figure 2. Pin Configuration
1
2
3
4
Rev. A | Page 6 of 16
(Not to Scale)
16
5
ADN2891
TOP VIEW
15
6
14
7
13
8
12
10
11
9
DRVCC
OUTP
OUTN
DRVEE