74ALVC16240MTD Fairchild Semiconductor, 74ALVC16240MTD Datasheet
74ALVC16240MTD
Specifications of 74ALVC16240MTD
Related parts for 74ALVC16240MTD
74ALVC16240MTD Summary of contents
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... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © ...
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Connection Diagram Functional Description The 74ALVC16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current ...
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AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol r 3.3V 0. FIGURE 2. Waveform ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...