74ALVC16240 Fairchild Semiconductor, 74ALVC16240 Datasheet

74ALVC16240

Manufacturer Part Number

74ALVC16240

Description

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74ALVC16240.pdf (6 pages)

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74ALVC16240MTD

74ALVC16240

Low Voltage 16-Bit Inverting Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16240 contains sixteen inverting buffers with 3-

STATE outputs to be employed as a memory and address

driver, clock driver, or bus oriented transmitter/receiver.

The device is nibble (4-bit) controlled. Each nibble has sep-

arate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74ALVC16240 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC16240 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O capability up to 3.6V.

Package Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500689

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

1.65V to 3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

Pin Names

3.0 ns max for 3.0V to 3.6V V

3.5 ns max for 2.3V to 2.7V V

6.0 ns max for 1.65V to 1.95V V

Human body model

Machine model

Package Descriptions

–I

–O

supply operation

Output Enable Input (Active LOW)

200V

2000V

through a pull-up resistor; the minimum

October 2001

Revised October 2001

Description

Outputs

Inputs

www.fairchildsemi.com

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74ALVC16240 Summary of contents

Page 1

... The device is nibble (4-bit) controlled. Each nibble has sep- arate 3-STATE control inputs which can be shorted together for full 16-bit operation. The 74ALVC16240 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74ALVC16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...

Page 2

... Connection Diagram Functional Description The 74ALVC16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are con- Logic Diagram www ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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