GAL16V8Z15QP Lattice Semiconductor Corp., GAL16V8Z15QP Datasheet

GAL16V8Z15QP

Manufacturer Part Number

GAL16V8Z15QP

Description

DIP20

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL16V8Z15QP.pdf (20 pages)

Specifications of GAL16V8Z15QP

Date_code

04+

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• ZERO POWER E

• HIGH PERFORMANCE E

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL16V8Z and GAL16V8ZD, at 100 μA standby current and

12ns propagation delay provides the highest speed and lowest

power combination PLD available in the market. The GAL16V8Z/

ZD is manufactured using Lattice Semiconductor's advanced zero

power E

Erasable (E

The GAL16V8Z uses Input Transition Detection (ITD) to put the

device in standby mode and is capable of emulating the full func-

tionality of the standard GAL16V8. The GAL16V8ZD utilizes a

dedicated power-down pin (DPP) to put the device in standby mode.

It has 15 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

16v8zzd_03

DESCRIPTION

Features

Description

— 100

— Input Transition Detection on GAL16V8Z

— Dedicated Power-down Pin on GAL16V8ZD

— Input and Output Latching During Power Down

— 12 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 8 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Output Drive

— UltraMOS

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Similar to Standard GAL16V8

— 100% Functional Testability

— Battery Powered Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

CELL TECHNOLOGY

CMOS process, which combines CMOS with Electrically

A Standby Current

) floating gate technology.

Advanced CMOS Technology

CMOS TECHNOLOGY

Functional Block Diagram

Pin Configuration

I/DPP

I/CLK

I/DPP

GAL16V8ZD

GAL16V8Z

Top View

PLCC

1 1

1 3

1 9

1 8

1 6

1 4

GAL16V8ZD

Zero Power E

I/O/Q

GAL16V8Z

I/D P P

I/C LK

G N D

CLK

OLMC

1 0

DIP/SOIC

December 1997

16V8ZD

16V8Z

CMOS PLD

GAL

2 0

1 5

1 1

I/O/Q

I/OE

V c c

I/ O/ Q

I/O/Q

I/ O/ Q

I /O E

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