GAL20RA10B20LP Lattice Semiconductor Corp., GAL20RA10B20LP Datasheet

GAL20RA10B20LP

Manufacturer Part Number

GAL20RA10B20LP

Description

DIP24

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL20RA10B20LP.pdf (15 pages)

Specifications of GAL20RA10B20LP

Date_code

04+

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• HIGH PERFORMANCE E

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

• ACTIVE PULL-UPS ON ALL PINS

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL20RA10 combines a high performance CMOS process

with electrically erasable (E

the highest speed performance available in the PLD market. Lattice

Semiconductor’s E

as 75mA typical I

when compared to bipolar counterparts. E

speed (<100ms) erase times providing the ability to reprogram,

reconfigure or test the devices quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL20RA10 is a direct parametric compatible CMOS

replacement for the PAL20RA10 device.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. Therefore, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20ra10_02

Features

— Independent Asynchronous Reset and Preset

Description

— 7.5 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 9 ns Maximum from Clock Input to Data Output

— TTL Compatible 8 mA Outputs

— UltraMOS

— 75mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

— Independent Programmable Clocks

— Registered or Combinatorial with Polarity

— Full Function and Parametric Compatibility with

— 100% Functional Testability

— State Machine Control

— Standard Logic Consolidation

— Multiple Clock Logic Designs

CELL TECHNOLOGY

PAL20RA10

Advanced CMOS Technology

which represents a substantial savings in power

CMOS circuitry achieves power levels as low

) floating gate technology to provide

CMOS

TECHNOLOGY

technology offers high

Functional Block Diagram

Pin Configuration

High-Speed Asynchronous E

GAL20RA10

Top View

PLCC

GAL20RA10

I/O/Q

Generic Array Logic™

GND

OLMC

20RA10

GAL

DIP

CMOS PLD

July 1997

I/O/Q

Vcc

I/O/Q

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