IS62WV25616BLL55BLI Integrated Silicon Solution, IS62WV25616BLL55BLI Datasheet

IS62WV25616BLL55BLI

Manufacturer Part Number

IS62WV25616BLL55BLI

Description

BGA48

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS62WV25616BLL55BI.pdf (10 pages)

Specifications of IS62WV25616BLL55BLI

Date_code

07+

Current page: 1 of 10
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IS62VV25616LL

FUNCTIONAL BLOCK DIAGRAM

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. B

08/07/02

FEATURES

• High-speed access time: 70, 85, ns

• CMOS low power operation

• Single 1.7V- 2.25 V

• Fully static operation: no clock or refresh

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP (Type II) and

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

256K x 16 LOW VOLTAGE, 1.8V ULTRA

LOW POWER CMOS STATIC RAM

– 36 mW (typical) operating

– 9 µW (typical) CMOS standby

required

48-pin mini BGA (7.2mm x 8.7mm)

Lower Byte

Upper Byte

I/O8-I/O15

power supply

I/O0-I/O7

A0-A17

GND

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

1-800-379-4774

DESCRIPTION

The

static RAMs organized as 262,144 words by 16 bits. They

are fabricated using

technology. This highly reliable process coupled with

innovative circuit design techniques, yields high-

performance and low power consumption devices.

For the IS62VV25616LL, when CE is HIGH (deselected)

or CE is low and both LB and UB are HIGH, the device

assumes a standby mode at which the power dissipation

can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs, CE and OE. The active LOW

Write Enable (WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (UB) and Lower

Byte (LB) access.

The IS62VV25616LL is packaged in the JEDEC standard

44-pin TSOP (Type II) and 48-pin mini BGA (7.2mm x 8.7mm).

MEMORY ARRAY

ISSI

COLUMN I/O

256K x 16

IS62VV25616LL is a high-speed, 4,194,304 bit

ISSI

's high-performance CMOS

ISSI

AUGUST 2002

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