AM28F256-150JC Advanced Micro Devices, AM28F256-150JC Datasheet

AM28F256-150JC

Manufacturer Part Number

AM28F256-150JC

Description

Manufacturer

Advanced Micro Devices

Datasheet

1.AM28F256-150JC.pdf (35 pages)

Specifications of AM28F256-150JC

Package

PLCC32

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Am28F256

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as

32 Kbytes of 8 bits each. AMD’s Flash memories offer

the most cost-effective and reliable read/write non-

volatile random access memory. The Am28F256 is

packaged in 32-pin PDIP , PLCC, and TSOP versions. It

is designed to be reprogrammed and erased in-system

or in standard EPROM programmers. The Am28F256

is erased when shipped from the factory.

The standard Am28F256 offers access times as fast as

70 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the Am28F256 has separate chip enable (CE

output enable (OE

AMD’s Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

Am28F256 uses a command register to manage this

functionality, while maintaining a standard JEDEC

Flash Standard 32-pin pinout. The command register

allows for 100% TTL level control inputs and fixed

power supply levels during erase and programming.

AMD’s Flash technology reliably stores memor y

contents even after 10,000 erase and program cycles.

Publication# 11560

Issue Date: January 1998

High performance

— 70 ns maximum access time

CMOS Low power consumption

— 30 mA maximum active current

— 100 µA maximum standby current

— No data retention power consumption

Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

— 32-pin TSOP

10,000 write/erase cycles minimum

Write and erase voltage 12.0 V 5%

FINAL

Rev: G Amendment/+2

) controls.

) and

The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina-

tion of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling. The Am28F256

uses a 12.0V 5% V

the Flasherase and Flashrite algorithms.

The highest degree of latch-up protection is achieved

with AMD’s proprietar y non-epi process. Latch-up

protection is provided for stresses up to 100 milliamps

on address and data pins from –1 V to V

The Am28F256 is byte programmable using 10 µs

programming pulses in accordance with AMD’s

Flashrite programming algorithm. The typical room

temperature programming time of the Am28F256 is a

half a second. The entire chip is bulk erased using

10 ms erase pulses according to AMD’s Flasherase

alrogithm. Typical erasure at room temperature is

accomplished in less than one second. The windowed

package and the 15-20 minutes required for EPROM

erasure using ultra-violet light are eliminated.

Latch-up protected to 100 mA

from –1 V to V

Flasherase Electrical Bulk Chip-Erase

— One second typical chip-erase

Flashrite Programming

— 10 µs typical byte-program

— 0.5 second typical chip program

Command register architecture for

microprocessor/microcontroller compatible

write interface

On-chip address and data latches

Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Automatic write/erase pulse stop timer

+1 V

high voltage input to perform

+1 V.

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