ORT8850H-1BM680 Lattice Semiconductor Corp., ORT8850H-1BM680 Datasheet

ORT8850H-1BM680

Manufacturer Part Number

ORT8850H-1BM680

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ORT8850H-1BM680.pdf (105 pages)

Specifications of ORT8850H-1BM680

Case

BGA

Date_code

04+

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October 2005

Introduction

Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro-

grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed

a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-

speed serial backplane data transfer. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC)

architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each

operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex

synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K

usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen-

dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for

HDLC for Internet Protocol (IP), designers can build a conﬁgurable interface retaining proven backplane

driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within

a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge

using our PCI soft core.

The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across

a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design

clock domains in a multiboard system, and fewer signals on the backplane. Network designers will beneﬁt from the

backplane transceiver as a network termination device. The backplane transceiver offers SONET scram-

bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus

the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all

SONET functionality is hidden from the user and no prior networking knowledge is required.

Table 1. ORCA ORT8850 Family – Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)

brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without

notice.

www.latticesemi.com

Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate

ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40%

EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage

and 6 PLLs.

ORT8850H

ORT8850L

Device

PFU Rows

Columns Total PFUs

PFU

2,024

624

FPGA Max

Eight-Channel x 850 Mbits/s Backplane Transceiver

User I/Os

278

297

Field-Programmable System Chip (FPSC)

16,192

LUTs

4,992

ORCA

Blocks

EBR

EBR Bits

148

(K)

ORT8850

Gates (K)

201 - 397

471 - 899

Data Sheet

ort8850_10

System

FPGA

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