LC74792JM Sanyo Semicon Device, LC74792JM Datasheet - Page 3

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LC74792JM

Manufacturer Part Number
LC74792JM
Description
VPS / PDC Slicer IC
Manufacturer
Sanyo Semicon Device
Datasheet
Pin Functions
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
SYNC
SEP
Xtal
CTRL1
CP
CTRL2
VCO
VCOR
SYN
SEP
SCLK
SEPC
CDLR
Xtal
V
V
V
V
Hout
DAV
Vout
RST
SIO
Pin
CS
SS
SS
DD
DD
OUT
OUT
OUT
IN
1
JDG
2
IN
IN
2
IN
1
Ground
Crystal oscillator connections
External synchronizing signal
discrimination output
Horizontal synchronizing signal output
Ground
Charge pump output
Oscillator control voltage input
Oscillator range adjustment
Data acquisition output
Sync separator circuit input
Slice level output
Composite synchronizing signal output
Vertical synchronizing signal input
Vertical synchronizing signal output
SEP
Clock phase adjustment
Reset input
Crystal element switching
Enable input pin
Data input/output pin
Clock input pin
Power supply (+5 V)
Power supply (+5 V)
IN
input control
Function
LC74792, 74792JM
Digital system ground
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
Enable input pin (hysteresis input)
Data input/output pin (hysteresis input)
Clock input pin (hysteresis input)
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Horizontal synchronizing signal output
Ground. (VCO circuit ground)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillation control voltage input
VCO oscillation range adjustment resistor connection
Outputs a low level when PDC/VPS data has been discriminated
Power supply (+5 V) (VCO system power supply)
Internal sync separator circuit video signal input
Slice level verification
Internal sync separator circuit composite synchronizing signal output
Inputs the vertical synchronizing signal by integrating the SEP
Applications must connect the SEP
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEP
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
Connection for the clock phase adjustment resistor
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Power supply. (+5 V: digital system power supply)
OUT
Description
pin to this pin through an integration circuit. If
OUT
pin output signal.
No. 5965-3/25
IN

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