LXT972 Level One, LXT972 Datasheet - Page 12

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

LXT972 3.3V Dual-Speed Fast Ethernet Transceiver
MII Data Interface
The LXT972 supports a standard Media Independent
Interface (MII). The MII consists of a data interface and a
management interface. The MII Data Interface passes data
between the LXT972 and a Media Access Controller
(MAC). Separate parallel buses are provided for transmit
and receive. This interface operates at either 10 Mbps or
100 Mbps.
operating conditions of the network link have been
determined. Refer to
additional details.
Configuration Management
Interface
The LXT972 provides both an MDIO interface and a
Hardware Control Interface for device configuration and
management.
Figure 2: Management Interface Read Frame Structure
Figure 3: Management Interface Write Frame Structure
12
MDIO Management Interface
M D I O
(Read)
M D C
The LXT972 supports the IEEE 802.3 MII
Management
Management Data Input/Output (MDIO) Interface.
This interface allows upper-layer devices to monitor
and control the state of the LXT972. The MDIO
interface consists of a physical connection, a specific
protocol that runs across the connection, and an
internal set of addressable registers.
(Write)
MDIO
High Z
M D C
Idle
P r e a m b l e
32 "1"s
The speed is set automatically, once the
Preamble
32 "1"s
Interface
0
0
S T
“MII Operation” on page 18
ST
1
1
1
also
0
O p C o d e
Op Code
0
1
known
Write
A 4
A4
P H Y A d d r e s s
PHY Address
A 3
A3
as
A 0
A0
the
for
Write
R 4
R4
Register Address
Register Address
R3
R 3
Some registers are required and their functions are
defined by the IEEE 802.3 standard. The LXT972
also supports additional registers for expanded
functionality. The LXT972 supports multiple internal
registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation,
where X is the register number (0-31) and Y is the bit
number (0-15).
The physical interface consists of a data line (MDIO)
and clock line (MDC). Operation of this interface is
controlled by the MDDIS input pin. When MDDIS is
High, the MDIO read and write operations are
disabled and the Hardware Control Interface provides
primary configuration control. When MDDIS is Low,
the MDIO port is enabled for both read and write
operations and the Hardware Control Interface is not
used.
MDIO Addressing
The protocol allows one controller to communicate
between two LXT972 chips. Pin ADDR0 is set high
or low to determine the chip address.
MDIO Frame Structure
The physical interface consists of a data line (MDIO)
and clock line (MDC). The frame structure is shown
in
timing is shown in
Figures 2 and 3
R0
R 0
1
Z
A r o u n d
Turn
Around
Turn
0
0
D 1 5
Table 32 on page
D15
(read and write). MDIO Interface
D 1 5
D 1 4
D14
D a t a
R e a d
D 1 4
Data
D 1
D1
D 1
D 0
D0
46.
Idle
Idle