LXT972 Level One, LXT972 Datasheet - Page 25

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

100BASE-X Protocol Sublayer
Operations
With respect to the 7-layer communications model, the
LXT972 is a Physical Layer 1 (PHY) device. The LXT972
implements the Physical Coding Sublayer (PCS), Physical
Medium Attachment (PMA), and Physical Medium
Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard.
paragraphs discuss LXT972 operation from the reference
model point of view.
Figure 18: Protocol Sublayers
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the
MII interface, as well as the 4B/5B encoding/
decoding function.
For 100TX operation, the PCS layer provides IDLE
symbols to the PMD-layer line driver as long as
TX_EN is de-asserted.
Sublayer
Sublayer
Sublayer
PMA
PMD
PCS
LXT972
The following
Serializer/De-serializer
Link/Carrier Detect
Encoder/Decoder
De-scrambler
Scrambler/
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a
/J/K symbol pair, also known as the Start-of-Stream
Delimiter (SSD), for the first two nibbles received
across the MII. The PCS layer continues to encode
the remaining MII data, following the coding in
Table 10 on page
then returns to supplying IDLE symbols to the line
driver.
In the receive direction, the PCS layer performs the
opposite function, substituting two preamble nibbles
for the SSD.
Dribble Bits
The LXT972 handles dribbles bits in all modes. If
between 1-4 dribble bits are received, the nibble will
be passed across the MII, padded with 1s if necessary.
If between 5-7 dribble bits are received, the second
nibble will not be sent onto the MII bus.
100BASE-TX
MII Interface
LXT972 Functional Description
26, until TX_EN is de-asserted. It
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