LXT972 Level One, LXT972 Datasheet - Page 6

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

LXT972 3.3V Dual-Speed Fast Ethernet Transceiver
Table 2:
6
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
LQFP
Pin#
60
59
58
57
56
55
45
46
47
48
49
53
54
52
62
63
3
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
TX_ER
RX_CLK
COL
CRS
MDDIS
Symbol
LXT972 MII Signal Descriptions
Type
O
O
O
O
O
O
O
I
I
I
I
1
Transmit Data. TXD is a bundle of parallel data signals that are driven by the
MAC. TXD<3:0> shall transition synchronously with respect to the TX_CLK.
TXD<0> is the least significant bit.
Transmit Enable. The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.
Receive Data. RXD is a bundle of parallel signals that transition synchronously with
respect to the RX_CLK. RXD<0> is the least significant bit.
Receive Data Valid. The LXT972 asserts this signal when it drives valid data on
RXD. This output is synchronous to RX_CLK.
Receive Error. Signals a receive error condition has occurred. This output is
synchronous to RX_CLK.
Transmit Error. Signals a transmit error condition. This signal must be
synchronized to TX_CLK.
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps operation.
Refer to
Collision Detected. The LXT972 asserts this output when a collision is detected.
This output remains High for the duration of the collision. This signal is
asynchronous and is inactive during full-duplex operation.
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972 asserts this
output when either transmitting or receiving data packets. During full-duplex
operation (bit 0.8 = 1), CRS is asserted during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier,
synchronous to RX_CLK.
Management Disable. When MDDIS is High, the MDIO is disabled from read and
write operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins con-
trol only the initial or “default” values of their respective register bits. After the
power-up/reset cycle is complete, bit control reverts to the MDIO serial channel.
SIGNAL DESCRIPTIONS
“Clock Requirements” on page 14
MII Control Interface Pins
Data Interface Pins
Signal Description
in the Functional Description section.