DG884AM VISHAY [Vishay Siliconix], DG884AM Datasheet - Page 7

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DG884AM

Manufacturer Part Number
DG884AM
Description
8 x 4 Wideband Video Crosspoint Array
Manufacturer
VISHAY [Vishay Siliconix]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DG884AM/883C
Manufacturer:
SC
Quantity:
500
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
Device A
Device B
Address
Address
TIMING DIAGRAMS
Device A
Device B
CS for
CS for
B
A
Address
Address
CS for
CS for
B
A
0
0
SALVO
SALVO
0
0
− B
− A
− B
− A
WR
Symbol
WR
RS
1
3
I/O
I/O
RS
1
3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
AW
CW
WC
WA
WP
WS
SW
AO
CO
SP
RS
CA
IO
IA
Output
Input
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
CA
t
IA
t
IO
t
CW
Select Output 1
t
O
t
C
AW
Select Input
Chip Select to WR
WR to Chip Select
Address to Output
CS to Address In
Address to Write
Write to Address
I/O to Address In
t
Parameter
WR to SALVO
SALVO to WR
SALVO Pulse
RS to SALVO
WP
I/O to Output
CS to Output
WR Pulse
Select Current
t
Event Latch 1
AO
Presetting Device A
Address Output 1
t
WA
Interrogating Device A
FIGURE 2. Output Timing Requirements
FIGURE 1. Input Timing Requirements
t
AO
Select Output 2
t
PARAMETER DEFINITIONS
AW
Select Input
t
WC
t
WA
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
WS
Minimum time address must be valid before WR goes high
Minimum time address must remain valid after WR pulse goes high
Minimum time of WR pulse width to write address into Next Event latches
Minimum time chip select must be valid before a WR pulse
Minimum time chip select must remain valid after WR pulse
Minimum time of SALVO pulse width
Minimum time from WR pulse to SALVO to load new address
Minimum time from SALVO pulse to WR to load current address
Minimum time I/O must be valid before address applied
Minimum time RS must be valid before SALVO pulse
Minimum time I/O must be valid before address output valid
Minimum time address B
Minimum time CS must be valid until A
Minimum time CS must be valid before address applied if I/O is high
Latch N
Out N
t
CA
t
SP
t
O
C
t
Interrogating Device B
SW
X
must be valid until address A
t
Select Current
AO
Event Latch
t
CW
Presetting Device B
t
Address Output
AW
Output N
Description
Input
X
output is valid
t
WA
t
AO
t
WS
t
A
t
Vishay Siliconix
C
IA
X
output valid
t
SP
t
RS
Don’t Care
Don’t Care
t
SW
DG884
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