MT88L89AC MITEL [Mitel Networks Corporation], MT88L89AC Datasheet

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MT88L89AC

Manufacturer Part Number
MT88L89AC
Description
3V Integrated DTMFTransceiver with Adaptive Micro Interface
Manufacturer
MITEL [Mitel Networks Corporation]
Datasheet
Features
Applications
Description
The MT88L89 is a monolithic DTMF transceiver with
call progress filter.
technology offering low power consumption and high
reliability.
TONE
OSC1
OSC2
IN+
GS
Central office quality DTMF transmitter/
receiver
Low voltage operation (2.7-3.6V)
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
DTMF transmitter/receiver power down via
register control
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
IN-
V
+
-
DD
Oscillator
Circuit
Circuit
V
Bias
Tone Burst
Gating Cct.
Ref
Tone
Filter
Dial
V
SS
It is fabricated in CMOS
Converters
High Group
Low Group
D/A
Control
Filter
Filter
Control
Logic
Logic
Advance Information
Figure 1 - Functional Block Diagram
ESt
Row and
Counters
Column
Converter
and Code
Algorithm
Digital
Steering
Logic
St/GT
The receiver section is based upon the industry
standard
transmitter
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features.
independently be powered down via register control.
Transmit Data
Receive Data
Register
Register
3V Integrated DTMF Transceiver
Register
Register
Status
Control
Register
MT88L89AE
MT88L89AC
MT88L89AS
MT88L89AN
MT88L89AP
Control
A
with Adaptive Micro Interface
B
MT8870
utilizes
The transmitter and
Ordering Information
-40°C to +85°C
DTMF
a
ISSUE 1
switched
Buffer
Control
Data
Interrupt
Bus
20 Pin Plastic DIP
20 Pin Ceramic DIP
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
Logic
I/O
receiver
MT88L89
capacitor
receiver
while
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
May 1995
may
4-125
D/A
the

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MT88L89AC Summary of contents

Page 1

... Ref SS 3V Integrated DTMF Transceiver Advance Information with Adaptive Micro Interface MT88L89AE MT88L89AC MT88L89AS MT88L89AN MT88L89AP The receiver section is based upon the industry standard transmitter converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing ...

Page 2

MT88L89 20 1 IN+ VDD 2 19 IN- St/ ESt 17 VRef VSS D2 15 OSC1 OSC2 TONE 8 IRQ/CP R/W/ DS/ ...

Page 3

Advance Information Pin Description Pin # Name Positive power supply (3V typ.). Connection. 8,9 3,5, 16, 10- 23- 25 Functional Description The MT88L89 Integrated DTMF Transceiver consists of ...

Page 4

MT88L89 F F DIGIT D LOW HIGH 3 697 1209 1 0 697 1336 2 0 697 1477 3 0 770 1209 4 0 770 1336 5 0 770 1477 6 0 852 1209 7 0 852 1336 8 1 ...

Page 5

Advance Information signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most C1 GTP (R1C1 GTA R = (R1R2) / (R1 ...

Page 6

MT88L89 EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION ...

Page 7

Advance Information The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data ...

Page 8

MT88L89 OUTPUT FREQUENCY (Hz) ACTIVE INPUT SPECIFIED ACTUAL L1 697 699.1 L2 770 766.2 L3 852 847.4 L4 941 948.0 H1 1209 1215.9 H2 1336 1331.7 1477 1471.9 H3 1633 1645.0 H4 Table 2. Actual Frequencies Versus Standard Requirements Distortion ...

Page 9

Advance Information (DS). When DS is low, Motorola processor operation is selected. Figure 17 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode ...

Page 10

MT88L89 Motorola Intel RS0 R Write to Transmit Data Register Read from Receive Data Register Write to Control Register Read from Status ...

Page 11

Advance Information BIT NAME b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, ...

Page 12

MT88L89 C1 R1 DTMF/CP INPUT R2 X-tal DTMF OUTPUT R L Notes: R1 100 374 3 (min 100 ...

Page 13

Advance Information A software reset must be included at the beginning of all programs to initialize the control registers after power up. Description: 1) Read Status Register 2) Write to Control Register 3) Write to Control Register 4) Write to ...

Page 14

MT88L89 Absolute Maximum Ratings Parameter 1 Power supply voltage Voltage on any pin 3 Current at any pin (Except Storage temperature 5 Package power dissipation * Exceeding these values may cause permanent damage. ...

Page 15

Advance Information Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (V Characteristics 1 Input leakage current 2 Input resistance 3 Input offset voltage 4 Power supply rejection 5 Common mode rejection 6 DC open loop voltage ...

Page 16

MT88L89 AC Electrical Characteristics Characteristics 1 Accept Bandwidth 2 Lower freq. (REJECT) 3 Upper freq. (REJECT) 4 Call progress tone detect level (total power) † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, ...

Page 17

Advance Information AC Electrical Characteristics Characteristics 1 DS/RD/WR clock frequency 2 DS/RD/WR cycle period 3 DS/RD/WR low pulse width 4 DS/RD/WR high pulse width 5 DS/RD/WR rise and fall time 6 R/W setup time 7 R/W hold time 8 Address ...

Page 18

MT88L89 DS Q clk* A0-A15 (RS0) R/W(read) Read Data (D3-D0) R/W (write) Write data (D3-D0 Q).Addr [MC6809 VMA.Addr [MC6800, MC6802] *microprocessor pin Figure 16 - MC6800/MC6802/MC6809 Timing Diagram t is from data to DS ...

Page 19

Advance Information ALE P0* A0-A7 (RS0, D0-D3 (Addr ALE.Addr * microprocessor pins Figure 18 - 8031/8051/8085 Read Timing Diagram ALE P0* (RS0, D0-D3 (Addr ALE.Addr * ...

Page 20

MT88L89 NOTES: 4-144 ...

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