MT88L89AC MITEL [Mitel Networks Corporation], MT88L89AC Datasheet - Page 2

• Manufacturer Part Number: MT88L89AC
• Description: 3V Integrated DTMFTransceiver with Adaptive Micro Interface
• Manufacturer: MITEL [Mitel Networks Corporation]

MT88L89
4-126
Pin Description
14-
20
10
11
12
13
17
18
19
1
2
3
4
5
6
7
8
9
R/W/WR
20 PIN CERDIP/PLASTIC DIP/SOIC
Pin #
TONE
OSC1
OSC2
18-
VRef
10
15
22
23
24
11
12
13
14
21
VSS
1
2
3
4
5
6
7
IN+
GS
CS
IN-
19-
28
12
13
14
15
17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is
18
22
26
27
1
2
4
6
7
8
9
10
1
2
3
4
5
6
7
8
9
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output
D0-D3
Name
OSC1
OSC2
TONE
St/GT
(WR)
R/W
RS0
V
V
ESt
GS
CS
IN+
IN-
Ref
SS
20
19
18
17
16
15
14
13
12
11
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage output (V
Ground (0V).
Oscillator input. This pin can also be driven directly by an external clock.
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
Chip Select input. This signal must be qualified externally by either address strobe
(AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
only required when the device is being accessed. TTL compatible.
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter, see Figure 8.
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
Early Steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
Steering Input/Guard Time output (bidirectional). A voltage greater than V
at St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
reset the external steering time-constant; its state is a function of ESt and the voltage
on St.
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
R/W/WR
OSC1
OSC2
TONE
VRef
VSS
IN+
Figure 2 - Pin Connections
GS
NC
NC
CS
IN-
TSt
frees the device to accept a new tone pair. The GT output acts to
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
DD
/2).
24
23
22
21
20
19
18
17
16
15
14
13
Description
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
OSC1
OSC2
VRef
VSS
NC
NC
NC
Advance Information
5
6
7
8
9
10
11
28 PIN PLCC
TSt
25
24
23
22
21
20
19
detected
NC
NC
NC
D3
D2
D1
D0